From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753866AbbKMIJV (ORCPT ); Fri, 13 Nov 2015 03:09:21 -0500 Received: from smtp.csie.ntu.edu.tw ([140.112.30.61]:39223 "EHLO smtp.csie.ntu.edu.tw" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752977AbbKMIJT (ORCPT ); Fri, 13 Nov 2015 03:09:19 -0500 MIME-Version: 1.0 In-Reply-To: References: <1446214865-3972-1-git-send-email-maxime.ripard@free-electrons.com> <1446214865-3972-6-git-send-email-maxime.ripard@free-electrons.com> From: Chen-Yu Tsai Date: Fri, 13 Nov 2015 16:08:53 +0800 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH 05/19] clk: sunxi: add DRAM gates To: Chen-Yu Tsai Cc: Maxime Ripard , Mike Turquette , Stephen Boyd , David Airlie , Thierry Reding , devicetree , linux-arm-kernel , linux-kernel , linux-clk , dri-devel , linux-sunxi , Laurent Pinchart , Hans de Goede , Alexander Kaplan , Wynter Woods , Boris Brezillon , Thomas Petazzoni , Rob Clark , Daniel Vetter Content-Type: text/plain; charset=UTF-8 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Nov 9, 2015 at 12:18 PM, Chen-Yu Tsai wrote: > On Fri, Oct 30, 2015 at 10:20 PM, Maxime Ripard > wrote: >> The Allwinner SoCs have a gate controller to gate the access to the DRAM >> clock to the some devices that need to access the DRAM directly (mostly >> display / image related IPs). >> >> Use a simple gates driver to support it. >> >> Signed-off-by: Maxime Ripard > > Acked-by: Chen-Yu Tsai > >> --- >> drivers/clk/sunxi/clk-simple-gates.c | 2 ++ >> 1 file changed, 2 insertions(+) >> >> diff --git a/drivers/clk/sunxi/clk-simple-gates.c b/drivers/clk/sunxi/clk-simple-gates.c >> index 0214c6548afd..5666c767fa14 100644 >> --- a/drivers/clk/sunxi/clk-simple-gates.c >> +++ b/drivers/clk/sunxi/clk-simple-gates.c >> @@ -112,6 +112,8 @@ CLK_OF_DECLARE(sun5i_a13_apb0, "allwinner,sun5i-a13-apb0-gates-clk", >> sunxi_simple_gates_init); >> CLK_OF_DECLARE(sun5i_a13_apb1, "allwinner,sun5i-a13-apb1-gates-clk", >> sunxi_simple_gates_init); >> +CLK_OF_DECLARE(sun5i_a13_dram, "allwinner,sun5i-a13-dram-gates-clk", >> + sunxi_simple_gates_init); Nit: Since the compatible added is sun5i, could you mention it in the commit message, to avoid confusion when we do this for the other families? Thanks >> CLK_OF_DECLARE(sun6i_a31_ahb1, "allwinner,sun6i-a31-ahb1-gates-clk", >> sunxi_simple_gates_init); >> CLK_OF_DECLARE(sun6i_a31_apb1, "allwinner,sun6i-a31-apb1-gates-clk", >> -- >> 2.6.2 >>