From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753462AbbKWHmS (ORCPT ); Mon, 23 Nov 2015 02:42:18 -0500 Received: from smtp.csie.ntu.edu.tw ([140.112.30.61]:42534 "EHLO smtp.csie.ntu.edu.tw" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752768AbbKWHmQ (ORCPT ); Mon, 23 Nov 2015 02:42:16 -0500 MIME-Version: 1.0 In-Reply-To: <20151105074730.fd6a9d57a1f2c7933478c680@free.fr> References: <1445964626-6484-1-git-send-email-jenskuske@gmail.com> <1445964626-6484-5-git-send-email-jenskuske@gmail.com> <13919923.o3Dj9msmoa@wuerfel> <20151104163014.GB6114@lukather> <20151105074730.fd6a9d57a1f2c7933478c680@free.fr> From: Chen-Yu Tsai Date: Mon, 23 Nov 2015 15:41:52 +0800 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [linux-sunxi] Re: [PATCH v4 4/6] reset: sunxi: Add Allwinner H3 bus resets To: moinejf@free.fr Cc: Maxime Ripard , Arnd Bergmann , devicetree , Vishnu Patekar , =?UTF-8?Q?Emilio_L=C3=B3pez?= , Michael Turquette , linux-sunxi , linux-kernel , Hans de Goede , Chen-Yu Tsai , Rob Herring , Jens Kuske , Philipp Zabel , Linus Walleij , linux-arm-kernel Content-Type: text/plain; charset=UTF-8 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Nov 5, 2015 at 2:47 PM, Jean-Francois Moine wrote: > On Wed, 4 Nov 2015 08:30:14 -0800 > Maxime Ripard wrote: > >> Hi Arnd, >> >> On Fri, Oct 30, 2015 at 09:27:03AM +0100, Arnd Bergmann wrote: >> > On Tuesday 27 October 2015 17:50:24 Jens Kuske wrote: >> > > >> > > +static int sun8i_h3_bus_reset_xlate(struct reset_controller_dev *rcdev, >> > > + const struct of_phandle_args *reset_spec) >> > > +{ >> > > + unsigned int index = reset_spec->args[0]; >> > > + >> > > + if (index < 96) >> > > + return index; >> > > + else if (index < 128) >> > > + return index + 32; >> > > + else if (index < 160) >> > > + return index + 64; >> > > + else >> > > + return -EINVAL; >> > > +} >> > > + >> > > >> > >> > This looks like you are doing something wrong and should either >> > put the actual number into DT, >> >> This is the actual number, except that there's some useless registers >> in between. Allwinner documents it like that: >> >> 0x0 Reset 0 >> 0x4 Reset 1 >> 0xc Reset 2 >> >> So we have to adjust the offset to account with the blank register in >> between (0x8). >> >> > or use a two-cell representation, with the first cell indicating the >> > block (0, 1 or 2), and the second cell the index. >> >> And the missing register is not a block either. >> >> That would also imply either changing the bindings of that driver (and >> all the current DTS that are using it), or introducing a whole new >> driver just to deal with some extraordinary offset calculation. > > In the H3, the holes are not used, but what would occur if these holes > would be used for some other purpose in future SoCs? Double mapping? We'd have a different compatible string for it. My suggestion for the resets is to just split them into 3 nodes: AHB (since AHB1 and AHB2 devices are mixed together in the bunch), APB1, and APB2 reset controls. This follows what we have for existing SoCs, and gets rid of the unused hole. We can use the existing "allwinner,sun6i-a31-clock-reset" and "allwinner,sun6i-a31-ahb1-reset" compatibles. Regards ChenYu