[PATCH v3 0/6] ARM: dts: sun8i: v3s: Enable video decoder

[PATCH v3 0/6] ARM: dts: sun8i: v3s: Enable video decoder

[Martin Cerveny]

First patch extends cedrus capability to all decoders
because V3s missing MPEG2 decoder.

Next two patches add system control node (SRAM C1) and 
next three patches add support for Cedrus VPU.

Tested on "Lichee Zero" V3s platform with testing LCD patch
( https://github.com/mcerveny/linux/tree/media_tree_for-v5.11e )
and V4L2 raw API testing utility (updated to v5.10)
( https://github.com/mcerveny/v4l2-request-test ):
- enabled LCD (DRM dual VI and sigle UI planes)
- added RGB panel
- enabled PWM
- need additional patch https://git.linuxtv.org/media_tree.git/commit/?h=fixes&id=9ac924b98728c3733c91c6c59fc410827d0da49f

There is low memory on V3s (64MB) and maximum must be available to CMA:
- CONFIG_CMA_SIZE_MBYTES=28
- add swap to swapout other processes
- decrease buffers in v4l2-request-test (.buffers_count from 16 to 8)

Only H.264 decoder working - MPEG and H.265 unsupported by V3s,
JPEG/MJPEG still unimplemented, encoder unimplemented

best regards,
Martin

Changes since v2:
- updated/rebased to https://git.linuxtv.org/hverkuil/media_tree.git/?h=for-v5.11e
- some parts of patches implemeted by others
- updated R40
Changes since v1:
- patch 0005 rename
- added testing description

Martin Cerveny (6):
  media: cedrus: Register all codecs as capability
  dt-bindings: sram: allwinner,sun4i-a10-system-control: Add V3s
    compatibles
  ARM: dts: sun8i: v3s: Add node for system control
  media: cedrus: Add support for V3s
  dt-bindings: media: cedrus: Add V3s compatible
  ARM: dts: sun8i: v3s: Add video engine node

 .../allwinner,sun4i-a10-video-engine.yaml     |  1 +
 .../allwinner,sun4i-a10-system-control.yaml   |  3 ++
 arch/arm/boot/dts/sun8i-v3s.dtsi              | 24 ++++++++++++++
 drivers/staging/media/sunxi/cedrus/cedrus.c   | 32 +++++++++++++++++--
 drivers/staging/media/sunxi/cedrus/cedrus.h   |  2 ++
 .../staging/media/sunxi/cedrus/cedrus_video.c |  2 ++
 6 files changed, 62 insertions(+), 2 deletions(-)

-- 
2.25.1

[PATCH v3 1/6] media: cedrus: Register all codecs as capability

[Martin Cerveny]

All codecs should have capabilities.
For example "Allwinner V3s" does not support "MPEG2".

Signed-off-by: Martin Cerveny <m.cerveny@computer.org>
---
 drivers/staging/media/sunxi/cedrus/cedrus.c   | 22 +++++++++++++++++--
 drivers/staging/media/sunxi/cedrus/cedrus.h   |  2 ++
 .../staging/media/sunxi/cedrus/cedrus_video.c |  2 ++
 3 files changed, 24 insertions(+), 2 deletions(-)

diff --git a/drivers/staging/media/sunxi/cedrus/cedrus.c b/drivers/staging/media/sunxi/cedrus/cedrus.c
index 9a102b7c1bb9..3487554fab68 100644
--- a/drivers/staging/media/sunxi/cedrus/cedrus.c
+++ b/drivers/staging/media/sunxi/cedrus/cedrus.c
@@ -486,47 +486,65 @@ static int cedrus_remove(struct platform_device *pdev)
 }
 
 static const struct cedrus_variant sun4i_a10_cedrus_variant = {
+	.capabilities	= CEDRUS_CAPABILITY_MPEG2_DEC |
+			  CEDRUS_CAPABILITY_H264_DEC,
 	.mod_rate	= 320000000,
 };
 
 static const struct cedrus_variant sun5i_a13_cedrus_variant = {
+	.capabilities	= CEDRUS_CAPABILITY_MPEG2_DEC |
+			  CEDRUS_CAPABILITY_H264_DEC,
 	.mod_rate	= 320000000,
 };
 
 static const struct cedrus_variant sun7i_a20_cedrus_variant = {
+	.capabilities	= CEDRUS_CAPABILITY_MPEG2_DEC |
+			  CEDRUS_CAPABILITY_H264_DEC,
 	.mod_rate	= 320000000,
 };
 
 static const struct cedrus_variant sun8i_a33_cedrus_variant = {
-	.capabilities	= CEDRUS_CAPABILITY_UNTILED,
+	.capabilities	= CEDRUS_CAPABILITY_UNTILED |
+			  CEDRUS_CAPABILITY_MPEG2_DEC |
+			  CEDRUS_CAPABILITY_H264_DEC,
 	.mod_rate	= 320000000,
 };
 
 static const struct cedrus_variant sun8i_h3_cedrus_variant = {
 	.capabilities	= CEDRUS_CAPABILITY_UNTILED |
+			  CEDRUS_CAPABILITY_MPEG2_DEC |
+			  CEDRUS_CAPABILITY_H264_DEC |
 			  CEDRUS_CAPABILITY_H265_DEC,
 	.mod_rate	= 402000000,
 };
 
 static const struct cedrus_variant sun8i_r40_cedrus_variant = {
-	.capabilities	= CEDRUS_CAPABILITY_UNTILED,
+	.capabilities	= CEDRUS_CAPABILITY_UNTILED |
+			  CEDRUS_CAPABILITY_MPEG2_DEC |
+			  CEDRUS_CAPABILITY_H264_DEC,
 	.mod_rate	= 297000000,
 };
 
 static const struct cedrus_variant sun50i_a64_cedrus_variant = {
 	.capabilities	= CEDRUS_CAPABILITY_UNTILED |
+			  CEDRUS_CAPABILITY_MPEG2_DEC |
+			  CEDRUS_CAPABILITY_H264_DEC |
 			  CEDRUS_CAPABILITY_H265_DEC,
 	.mod_rate	= 402000000,
 };
 
 static const struct cedrus_variant sun50i_h5_cedrus_variant = {
 	.capabilities	= CEDRUS_CAPABILITY_UNTILED |
+			  CEDRUS_CAPABILITY_MPEG2_DEC |
+			  CEDRUS_CAPABILITY_H264_DEC |
 			  CEDRUS_CAPABILITY_H265_DEC,
 	.mod_rate	= 402000000,
 };
 
 static const struct cedrus_variant sun50i_h6_cedrus_variant = {
 	.capabilities	= CEDRUS_CAPABILITY_UNTILED |
+			  CEDRUS_CAPABILITY_MPEG2_DEC |
+			  CEDRUS_CAPABILITY_H264_DEC |
 			  CEDRUS_CAPABILITY_H265_DEC,
 	.quirks		= CEDRUS_QUIRK_NO_DMA_OFFSET,
 	.mod_rate	= 600000000,
diff --git a/drivers/staging/media/sunxi/cedrus/cedrus.h b/drivers/staging/media/sunxi/cedrus/cedrus.h
index 93c843ae14bb..30cdb15d6800 100644
--- a/drivers/staging/media/sunxi/cedrus/cedrus.h
+++ b/drivers/staging/media/sunxi/cedrus/cedrus.h
@@ -28,6 +28,8 @@
 
 #define CEDRUS_CAPABILITY_UNTILED	BIT(0)
 #define CEDRUS_CAPABILITY_H265_DEC	BIT(1)
+#define CEDRUS_CAPABILITY_H264_DEC	BIT(2)
+#define CEDRUS_CAPABILITY_MPEG2_DEC	BIT(3)
 
 #define CEDRUS_QUIRK_NO_DMA_OFFSET	BIT(0)
 
diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_video.c b/drivers/staging/media/sunxi/cedrus/cedrus_video.c
index 911f607d9b09..bdca23fc214b 100644
--- a/drivers/staging/media/sunxi/cedrus/cedrus_video.c
+++ b/drivers/staging/media/sunxi/cedrus/cedrus_video.c
@@ -38,10 +38,12 @@ static struct cedrus_format cedrus_formats[] = {
 	{
 		.pixelformat	= V4L2_PIX_FMT_MPEG2_SLICE,
 		.directions	= CEDRUS_DECODE_SRC,
+		.capabilities	= CEDRUS_CAPABILITY_MPEG2_DEC,
 	},
 	{
 		.pixelformat	= V4L2_PIX_FMT_H264_SLICE,
 		.directions	= CEDRUS_DECODE_SRC,
+		.capabilities	= CEDRUS_CAPABILITY_H264_DEC,
 	},
 	{
 		.pixelformat	= V4L2_PIX_FMT_HEVC_SLICE,
-- 
2.25.1

[PATCH v3 2/6] dt-bindings: sram: allwinner,sun4i-a10-system-control: Add V3s compatibles

[Martin Cerveny]

Allwinner V3s has system control similar to that in H3.
Add compatibles for system control with SRAM C1 region.

Signed-off-by: Martin Cerveny <m.cerveny@computer.org>
---
 .../bindings/sram/allwinner,sun4i-a10-system-control.yaml      | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/Documentation/devicetree/bindings/sram/allwinner,sun4i-a10-system-control.yaml b/Documentation/devicetree/bindings/sram/allwinner,sun4i-a10-system-control.yaml
index b66a07e21d1e..bdd352b01434 100644
--- a/Documentation/devicetree/bindings/sram/allwinner,sun4i-a10-system-control.yaml
+++ b/Documentation/devicetree/bindings/sram/allwinner,sun4i-a10-system-control.yaml
@@ -92,6 +92,9 @@ patternProperties:
               - items:
                   - const: allwinner,sun8i-h3-sram-c1
                   - const: allwinner,sun4i-a10-sram-c1
+              - items:
+                  - const: allwinner,sun8i-v3s-sram-c1
+                  - const: allwinner,sun4i-a10-sram-c1
               - items:
                   - const: allwinner,sun8i-r40-sram-c1
                   - const: allwinner,sun4i-a10-sram-c1
-- 
2.25.1

[PATCH v3 3/6] ARM: dts: sun8i: v3s: Add node for system control

[Martin Cerveny]

Allwinner V3s has system control and SRAM C1 region similar to H3.

Signed-off-by: Martin Cerveny <m.cerveny@computer.org>
---
 arch/arm/boot/dts/sun8i-v3s.dtsi | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i-v3s.dtsi
index 0c7341676921..70193512c222 100644
--- a/arch/arm/boot/dts/sun8i-v3s.dtsi
+++ b/arch/arm/boot/dts/sun8i-v3s.dtsi
@@ -161,6 +161,20 @@ syscon: system-control@1c00000 {
 			#address-cells = <1>;
 			#size-cells = <1>;
 			ranges;
+
+			sram_c: sram@1d00000 {
+				compatible = "mmio-sram";
+				reg = <0x01d00000 0x80000>;
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges = <0 0x01d00000 0x80000>;
+
+				ve_sram: sram-section@0 {
+					compatible = "allwinner,sun8i-v3s-sram-c1",
+						     "allwinner,sun4i-a10-sram-c1";
+					reg = <0x000000 0x80000>;
+				};
+			};
 		};
 
 		tcon0: lcd-controller@1c0c000 {
-- 
2.25.1

[PATCH v3 4/6] media: cedrus: Add support for V3s

[Martin Cerveny]

V3s video engine runs at lower speed and support video decoder
for H.264 and JPEG/MJPEG only.

Signed-off-by: Martin Cerveny <m.cerveny@computer.org>
---
 drivers/staging/media/sunxi/cedrus/cedrus.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/drivers/staging/media/sunxi/cedrus/cedrus.c b/drivers/staging/media/sunxi/cedrus/cedrus.c
index 3487554fab68..ee4e21b29374 100644
--- a/drivers/staging/media/sunxi/cedrus/cedrus.c
+++ b/drivers/staging/media/sunxi/cedrus/cedrus.c
@@ -518,6 +518,12 @@ static const struct cedrus_variant sun8i_h3_cedrus_variant = {
 	.mod_rate	= 402000000,
 };
 
+static const struct cedrus_variant sun8i_v3s_cedrus_variant = {
+	.capabilities	= CEDRUS_CAPABILITY_UNTILED |
+			  CEDRUS_CAPABILITY_H264_DEC,
+	.mod_rate	= 297000000,
+};
+
 static const struct cedrus_variant sun8i_r40_cedrus_variant = {
 	.capabilities	= CEDRUS_CAPABILITY_UNTILED |
 			  CEDRUS_CAPABILITY_MPEG2_DEC |
@@ -571,6 +577,10 @@ static const struct of_device_id cedrus_dt_match[] = {
 		.compatible = "allwinner,sun8i-h3-video-engine",
 		.data = &sun8i_h3_cedrus_variant,
 	},
+	{
+		.compatible = "allwinner,sun8i-v3s-video-engine",
+		.data = &sun8i_v3s_cedrus_variant,
+	},
 	{
 		.compatible = "allwinner,sun8i-r40-video-engine",
 		.data = &sun8i_r40_cedrus_variant,
-- 
2.25.1

[PATCH v3 5/6] dt-bindings: media: cedrus: Add V3s compatible

[Martin Cerveny]

Allwinner V3s SoC contains video engine. Add compatible for it.

Signed-off-by: Martin Cerveny <m.cerveny@computer.org>
---
 .../bindings/media/allwinner,sun4i-a10-video-engine.yaml         | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/media/allwinner,sun4i-a10-video-engine.yaml b/Documentation/devicetree/bindings/media/allwinner,sun4i-a10-video-engine.yaml
index 0d58bbcd24d3..2f7058f7760c 100644
--- a/Documentation/devicetree/bindings/media/allwinner,sun4i-a10-video-engine.yaml
+++ b/Documentation/devicetree/bindings/media/allwinner,sun4i-a10-video-engine.yaml
@@ -18,6 +18,7 @@ properties:
       - allwinner,sun7i-a20-video-engine
       - allwinner,sun8i-a33-video-engine
       - allwinner,sun8i-h3-video-engine
+      - allwinner,sun8i-v3s-video-engine
       - allwinner,sun8i-r40-video-engine
       - allwinner,sun50i-a64-video-engine
       - allwinner,sun50i-h5-video-engine
-- 
2.25.1

[PATCH v3 6/6] ARM: dts: sun8i: v3s: Add video engine node

[Martin Cerveny]

Allwinner V3S SoC has a video engine.
Add a node for it.

Signed-off-by: Martin Cerveny <m.cerveny@computer.org>
---
 arch/arm/boot/dts/sun8i-v3s.dtsi | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i-v3s.dtsi
index 70193512c222..e8f304125e2d 100644
--- a/arch/arm/boot/dts/sun8i-v3s.dtsi
+++ b/arch/arm/boot/dts/sun8i-v3s.dtsi
@@ -211,6 +211,16 @@ tcon0_out: port@1 {
 			};
 		};
 
+		video-codec@1c0e000 {
+			compatible = "allwinner,sun8i-v3s-video-engine";
+			reg = <0x01c0e000 0x1000>;
+			clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>,
+				 <&ccu CLK_DRAM_VE>;
+			clock-names = "ahb", "mod", "ram";
+			resets = <&ccu RST_BUS_VE>;
+			interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
+			allwinner,sram = <&ve_sram 1>;
+		};
 
 		mmc0: mmc@1c0f000 {
 			compatible = "allwinner,sun7i-a20-mmc";
-- 
2.25.1

Re: [PATCH v3 5/6] dt-bindings: media: cedrus: Add V3s compatible

[Chen-Yu Tsai]

On Mon, Nov 16, 2020 at 8:58 PM Martin Cerveny <m.cerveny@computer.org> wrote:
>
> Allwinner V3s SoC contains video engine. Add compatible for it.
>
> Signed-off-by: Martin Cerveny <m.cerveny@computer.org>

Acked-by: Chen-Yu Tsai <wens@csie.org>

Re: [PATCH v3 6/6] ARM: dts: sun8i: v3s: Add video engine node

[Chen-Yu Tsai]

On Mon, Nov 16, 2020 at 8:58 PM Martin Cerveny <m.cerveny@computer.org> wrote:
>
> Allwinner V3S SoC has a video engine.
> Add a node for it.
>
> Signed-off-by: Martin Cerveny <m.cerveny@computer.org>

Acked-by: Chen-Yu Tsai <wens@csie.org>

Re: [PATCH v3 2/6] dt-bindings: sram: allwinner, sun4i-a10-system-control: Add V3s compatibles

[Rob Herring]

On Mon, 16 Nov 2020 13:56:13 +0100, Martin Cerveny wrote:
> Allwinner V3s has system control similar to that in H3.
> Add compatibles for system control with SRAM C1 region.
> 
> Signed-off-by: Martin Cerveny <m.cerveny@computer.org>
> ---
>  .../bindings/sram/allwinner,sun4i-a10-system-control.yaml      | 3 +++
>  1 file changed, 3 insertions(+)
> 

Reviewed-by: Rob Herring <robh@kernel.org>

Re: [PATCH v3 5/6] dt-bindings: media: cedrus: Add V3s compatible

[Rob Herring]

On Mon, 16 Nov 2020 13:56:16 +0100, Martin Cerveny wrote:
> Allwinner V3s SoC contains video engine. Add compatible for it.
> 
> Signed-off-by: Martin Cerveny <m.cerveny@computer.org>
> ---
>  .../bindings/media/allwinner,sun4i-a10-video-engine.yaml         | 1 +
>  1 file changed, 1 insertion(+)
> 

Acked-by: Rob Herring <robh@kernel.org>

Re: [PATCH v3 0/6] ARM: dts: sun8i: v3s: Enable video decoder

[Hans Verkuil]

Hi Martin, Maxime,

On 16/11/2020 13:56, Martin Cerveny wrote:
> First patch extends cedrus capability to all decoders
> because V3s missing MPEG2 decoder.
> 
> Next two patches add system control node (SRAM C1) and 
> next three patches add support for Cedrus VPU.

I've picked up patches 1, 4 and 5 for the media subsystem.
Maxime, can you pick up the other three?

Thanks!

	Hans

> 
> Tested on "Lichee Zero" V3s platform with testing LCD patch
> ( https://github.com/mcerveny/linux/tree/media_tree_for-v5.11e )
> and V4L2 raw API testing utility (updated to v5.10)
> ( https://github.com/mcerveny/v4l2-request-test ):
> - enabled LCD (DRM dual VI and sigle UI planes)
> - added RGB panel
> - enabled PWM
> - need additional patch https://git.linuxtv.org/media_tree.git/commit/?h=fixes&id=9ac924b98728c3733c91c6c59fc410827d0da49f
> 
> There is low memory on V3s (64MB) and maximum must be available to CMA:
> - CONFIG_CMA_SIZE_MBYTES=28
> - add swap to swapout other processes
> - decrease buffers in v4l2-request-test (.buffers_count from 16 to 8)
> 
> Only H.264 decoder working - MPEG and H.265 unsupported by V3s,
> JPEG/MJPEG still unimplemented, encoder unimplemented
> 
> best regards,
> Martin
> 
> Changes since v2:
> - updated/rebased to https://git.linuxtv.org/hverkuil/media_tree.git/?h=for-v5.11e
> - some parts of patches implemeted by others
> - updated R40
> Changes since v1:
> - patch 0005 rename
> - added testing description
> 
> Martin Cerveny (6):
>   media: cedrus: Register all codecs as capability
>   dt-bindings: sram: allwinner,sun4i-a10-system-control: Add V3s
>     compatibles
>   ARM: dts: sun8i: v3s: Add node for system control
>   media: cedrus: Add support for V3s
>   dt-bindings: media: cedrus: Add V3s compatible
>   ARM: dts: sun8i: v3s: Add video engine node
> 
>  .../allwinner,sun4i-a10-video-engine.yaml     |  1 +
>  .../allwinner,sun4i-a10-system-control.yaml   |  3 ++
>  arch/arm/boot/dts/sun8i-v3s.dtsi              | 24 ++++++++++++++
>  drivers/staging/media/sunxi/cedrus/cedrus.c   | 32 +++++++++++++++++--
>  drivers/staging/media/sunxi/cedrus/cedrus.h   |  2 ++
>  .../staging/media/sunxi/cedrus/cedrus_video.c |  2 ++
>  6 files changed, 62 insertions(+), 2 deletions(-)
> 

Re: [PATCH v3 3/6] ARM: dts: sun8i: v3s: Add node for system control

[Chen-Yu Tsai]

Hi,

On Mon, Nov 16, 2020 at 8:57 PM Martin Cerveny <m.cerveny@computer.org> wrote:
>
> Allwinner V3s has system control and SRAM C1 region similar to H3.
>
> Signed-off-by: Martin Cerveny <m.cerveny@computer.org>
> ---
>  arch/arm/boot/dts/sun8i-v3s.dtsi | 14 ++++++++++++++
>  1 file changed, 14 insertions(+)
>
> diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i-v3s.dtsi
> index 0c7341676921..70193512c222 100644
> --- a/arch/arm/boot/dts/sun8i-v3s.dtsi
> +++ b/arch/arm/boot/dts/sun8i-v3s.dtsi
> @@ -161,6 +161,20 @@ syscon: system-control@1c00000 {
>                         #address-cells = <1>;
>                         #size-cells = <1>;
>                         ranges;
> +
> +                       sram_c: sram@1d00000 {
> +                               compatible = "mmio-sram";
> +                               reg = <0x01d00000 0x80000>;

How was this address derived? Did you check that there is actually SRAM here?

ChenYu

> +                               #address-cells = <1>;
> +                               #size-cells = <1>;
> +                               ranges = <0 0x01d00000 0x80000>;
> +
> +                               ve_sram: sram-section@0 {
> +                                       compatible = "allwinner,sun8i-v3s-sram-c1",
> +                                                    "allwinner,sun4i-a10-sram-c1";
> +                                       reg = <0x000000 0x80000>;
> +                               };
> +                       };
>                 };
>
>                 tcon0: lcd-controller@1c0c000 {
> --
> 2.25.1
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Re: [PATCH v3 3/6] ARM: dts: sun8i: v3s: Add node for system control

[Martin Cerveny]

Hello.

On Thu, 3 Dec 2020, Chen-Yu Tsai wrote:

> Hi,
>
> On Mon, Nov 16, 2020 at 8:57 PM Martin Cerveny <m.cerveny@computer.org> wrote:
>>
>> Allwinner V3s has system control and SRAM C1 region similar to H3.
>>
>> Signed-off-by: Martin Cerveny <m.cerveny@computer.org>
>> ---
>>  arch/arm/boot/dts/sun8i-v3s.dtsi | 14 ++++++++++++++
>>  1 file changed, 14 insertions(+)
>>
>> diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i-v3s.dtsi
>> index 0c7341676921..70193512c222 100644
>> --- a/arch/arm/boot/dts/sun8i-v3s.dtsi
>> +++ b/arch/arm/boot/dts/sun8i-v3s.dtsi
>> @@ -161,6 +161,20 @@ syscon: system-control@1c00000 {
>>                         #address-cells = <1>;
>>                         #size-cells = <1>;
>>                         ranges;
>> +
>> +                       sram_c: sram@1d00000 {
>> +                               compatible = "mmio-sram";
>> +                               reg = <0x01d00000 0x80000>;
>
> How was this address derived? Did you check that there is actually SRAM here?

Yes, I did some checking (mmap). But I repeated measurement and found 
mirrored regions:

- SRAM_C is mirrored from 0x0000_4000 (primary location) to 0x01d0_4000 (size 0xb000)
   (probably exact size is 0xb0c0)
- rest of 0x01d0_0000 are discontinuously filled with R/W register sets
   (probably some internals registers from VE) that I thought to be SRAM too
- register SRAM_CTRL_REG0==0x01c00_0000 (value 0x7fff_ffff) switch whole
   region 0x01d0_0000-0x01df_ffff __AND__ 0x0000_4000-0x0000_ffff
- VE/cedrus code use this regions indirectly
   (VE_AVC_SRAM_PORT_OFFSET/VE_AVC_SRAM_PORT_DATA...)
   and it is not influenced by "true" SRAM mapping or size

-> so I suppose to better use only SRAM_C lower definition:

---
diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i-v3s.dtsi
index e8f304125e2d..90d703e5b73b 100644
--- a/arch/arm/boot/dts/sun8i-v3s.dtsi
+++ b/arch/arm/boot/dts/sun8i-v3s.dtsi
@@ -162,17 +162,17 @@ syscon: system-control@1c00000 {
  			#size-cells = <1>;
  			ranges;

-			sram_c: sram@1d00000 {
+			sram_c: sram@4000 {
  				compatible = "mmio-sram";
-				reg = <0x01d00000 0x80000>;
+				reg = <0x4000 0xb000>;
  				#address-cells = <1>;
  				#size-cells = <1>;
-				ranges = <0 0x01d00000 0x80000>;
+				ranges = <0 0 0x4000 0xb000>;

  				ve_sram: sram-section@0 {
  					compatible = "allwinner,sun8i-v3s-sram-c1",
  						     "allwinner,sun4i-a10-sram-c1";
-					reg = <0x000000 0x80000>;
+					reg = <0x0 0xb000>;
  				};
  			};
  		};
---

Does someone have accessible specific documentation of VE/cedrus for V3s ?

Regards, Martin

> ChenYu
>
>> +                               #address-cells = <1>;
>> +                               #size-cells = <1>;
>> +                               ranges = <0 0x01d00000 0x80000>;
>> +
>> +                               ve_sram: sram-section@0 {
>> +                                       compatible = "allwinner,sun8i-v3s-sram-c1",
>> +                                                    "allwinner,sun4i-a10-sram-c1";
>> +                                       reg = <0x000000 0x80000>;
>> +                               };
>> +                       };
>>                 };
>>
>>                 tcon0: lcd-controller@1c0c000 {
>> --
>> 2.25.1
>>
>>
>> _______________________________________________
>> linux-arm-kernel mailing list
>> linux-arm-kernel@lists.infradead.org
>> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>

Re: [PATCH v3 3/6] ARM: dts: sun8i: v3s: Add node for system control

[Chen-Yu Tsai]

On Fri, Dec 4, 2020 at 12:25 AM Martin Cerveny <martin@c-home.cz> wrote:
>
> Hello.
>
> On Thu, 3 Dec 2020, Chen-Yu Tsai wrote:
>
> > Hi,
> >
> > On Mon, Nov 16, 2020 at 8:57 PM Martin Cerveny <m.cerveny@computer.org> wrote:
> >>
> >> Allwinner V3s has system control and SRAM C1 region similar to H3.
> >>
> >> Signed-off-by: Martin Cerveny <m.cerveny@computer.org>
> >> ---
> >>  arch/arm/boot/dts/sun8i-v3s.dtsi | 14 ++++++++++++++
> >>  1 file changed, 14 insertions(+)
> >>
> >> diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i-v3s.dtsi
> >> index 0c7341676921..70193512c222 100644
> >> --- a/arch/arm/boot/dts/sun8i-v3s.dtsi
> >> +++ b/arch/arm/boot/dts/sun8i-v3s.dtsi
> >> @@ -161,6 +161,20 @@ syscon: system-control@1c00000 {
> >>                         #address-cells = <1>;
> >>                         #size-cells = <1>;
> >>                         ranges;
> >> +
> >> +                       sram_c: sram@1d00000 {
> >> +                               compatible = "mmio-sram";
> >> +                               reg = <0x01d00000 0x80000>;
> >
> > How was this address derived? Did you check that there is actually SRAM here?
>
> Yes, I did some checking (mmap). But I repeated measurement and found
> mirrored regions:
>
> - SRAM_C is mirrored from 0x0000_4000 (primary location) to 0x01d0_4000 (size 0xb000)
>    (probably exact size is 0xb0c0)
> - rest of 0x01d0_0000 are discontinuously filled with R/W register sets
>    (probably some internals registers from VE) that I thought to be SRAM too
> - register SRAM_CTRL_REG0==0x01c00_0000 (value 0x7fff_ffff) switch whole
>    region 0x01d0_0000-0x01df_ffff __AND__ 0x0000_4000-0x0000_ffff
> - VE/cedrus code use this regions indirectly
>    (VE_AVC_SRAM_PORT_OFFSET/VE_AVC_SRAM_PORT_DATA...)
>    and it is not influenced by "true" SRAM mapping or size

Could you add this to your commit log? That would make the information
available to others, and you could mention that you only added the
location that is contiguous SRAM without the interspersed registers.

So based on this, and what we've seen with the H616, I'm guessing
0x01d0_0000 - 0x01df_ffff exposes all the internal guts of the VE,
while SRAM C @ 0x4000 just maps a small portion out.

> -> so I suppose to better use only SRAM_C lower definition:

Yes that would be more appropriate, as it matches the manual, and as you
mentioned, is *real* SRAM.

> ---
> diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i-v3s.dtsi
> index e8f304125e2d..90d703e5b73b 100644
> --- a/arch/arm/boot/dts/sun8i-v3s.dtsi
> +++ b/arch/arm/boot/dts/sun8i-v3s.dtsi
> @@ -162,17 +162,17 @@ syscon: system-control@1c00000 {
>                         #size-cells = <1>;
>                         ranges;
>
> -                       sram_c: sram@1d00000 {
> +                       sram_c: sram@4000 {
>                                 compatible = "mmio-sram";
> -                               reg = <0x01d00000 0x80000>;
> +                               reg = <0x4000 0xb000>;
>                                 #address-cells = <1>;
>                                 #size-cells = <1>;
> -                               ranges = <0 0x01d00000 0x80000>;
> +                               ranges = <0 0 0x4000 0xb000>;
>
>                                 ve_sram: sram-section@0 {
>                                         compatible = "allwinner,sun8i-v3s-sram-c1",
>                                                      "allwinner,sun4i-a10-sram-c1";
> -                                       reg = <0x000000 0x80000>;
> +                                       reg = <0x0 0xb000>;
>                                 };
>                         };
>                 };
> ---
>
> Does someone have accessible specific documentation of VE/cedrus for V3s ?

I doubt such information exists.


Regards
ChenYu

> Regards, Martin
>
> > ChenYu
> >
> >> +                               #address-cells = <1>;
> >> +                               #size-cells = <1>;
> >> +                               ranges = <0 0x01d00000 0x80000>;
> >> +
> >> +                               ve_sram: sram-section@0 {
> >> +                                       compatible = "allwinner,sun8i-v3s-sram-c1",
> >> +                                                    "allwinner,sun4i-a10-sram-c1";
> >> +                                       reg = <0x000000 0x80000>;
> >> +                               };
> >> +                       };
> >>                 };
> >>
> >>                 tcon0: lcd-controller@1c0c000 {
> >> --
> >> 2.25.1
> >>
> >>
> >> _______________________________________________
> >> linux-arm-kernel mailing list
> >> linux-arm-kernel@lists.infradead.org
> >> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
> >

Re: [PATCH v3 3/6] ARM: dts: sun8i: v3s: Add node for system control

[Samuel Holland]

On 12/3/20 10:44 AM, Chen-Yu Tsai wrote:
> On Fri, Dec 4, 2020 at 12:25 AM Martin Cerveny <martin@c-home.cz> wrote:
>>
>> Hello.
>>
>> On Thu, 3 Dec 2020, Chen-Yu Tsai wrote:
>>
>>> Hi,
>>>
>>> On Mon, Nov 16, 2020 at 8:57 PM Martin Cerveny <m.cerveny@computer.org> wrote:
>>>>
>>>> Allwinner V3s has system control and SRAM C1 region similar to H3.
>>>>
>>>> Signed-off-by: Martin Cerveny <m.cerveny@computer.org>
>>>> ---
>>>>  arch/arm/boot/dts/sun8i-v3s.dtsi | 14 ++++++++++++++
>>>>  1 file changed, 14 insertions(+)
>>>>
>>>> diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i-v3s.dtsi
>>>> index 0c7341676921..70193512c222 100644
>>>> --- a/arch/arm/boot/dts/sun8i-v3s.dtsi
>>>> +++ b/arch/arm/boot/dts/sun8i-v3s.dtsi
>>>> @@ -161,6 +161,20 @@ syscon: system-control@1c00000 {
>>>>                         #address-cells = <1>;
>>>>                         #size-cells = <1>;
>>>>                         ranges;
>>>> +
>>>> +                       sram_c: sram@1d00000 {
>>>> +                               compatible = "mmio-sram";
>>>> +                               reg = <0x01d00000 0x80000>;
>>>
>>> How was this address derived? Did you check that there is actually SRAM here?
>>
>> Yes, I did some checking (mmap). But I repeated measurement and found
>> mirrored regions:
>>
>> - SRAM_C is mirrored from 0x0000_4000 (primary location) to 0x01d0_4000 (size 0xb000)
>>    (probably exact size is 0xb0c0)
>> - rest of 0x01d0_0000 are discontinuously filled with R/W register sets
>>    (probably some internals registers from VE) that I thought to be SRAM too
>> - register SRAM_CTRL_REG0==0x01c00_0000 (value 0x7fff_ffff) switch whole
>>    region 0x01d0_0000-0x01df_ffff __AND__ 0x0000_4000-0x0000_ffff
>> - VE/cedrus code use this regions indirectly
>>    (VE_AVC_SRAM_PORT_OFFSET/VE_AVC_SRAM_PORT_DATA...)
>>    and it is not influenced by "true" SRAM mapping or size
> 
> Could you add this to your commit log? That would make the information
> available to others, and you could mention that you only added the
> location that is contiguous SRAM without the interspersed registers.
> 
> So based on this, and what we've seen with the H616, I'm guessing
> 0x01d0_0000 - 0x01df_ffff exposes all the internal guts of the VE,
> while SRAM C @ 0x4000 just maps a small portion out.
> 
>> -> so I suppose to better use only SRAM_C lower definition:
> 
> Yes that would be more appropriate, as it matches the manual, and as you
> mentioned, is *real* SRAM.

My reading of the manual and comments in the BSP U-Boot is that the high
address near the VE registers is the "real" address. The alternate SRAM
mapping just past the end of SRAM A1 exists specifically so the boot ROM
can load boot0/TOC0 images larger than would fit in SRAM A1.

I don't have a copy of the V3s BROM, but here's the logic from the
beginning of the H6 SBROM, which first enables the VE bus clock and
reset before mapping the SRAM:

; VE_BGR_REG |= BIT(16)
     2dc:  e59f113c  ldr r1, [pc, #316] ; 420
     2e0:  e5912000  ldr r2, [r1]
     2e4:  e3a03801  mov r3, #65536 ; 0x10000
     2e8:  e1822003  orr r2, r2, r3
     2ec:  e5812000  str r2, [r1]
; VE_BGR_REG |= BIT(0)
     2f0:  e59f1128  ldr r1, [pc, #296] ; 420
     2f4:  e5912000  ldr r2, [r1]
     2f8:  e3a03001  mov r3, #1
     2fc:  e1822003  orr r2, r2, r3
     300:  e5812000  str r2, [r1]
; SRAM_CTRL_REG0 &= BIT(31)
     304:  e3a01403  mov r1, #50331648 ; 0x3000000
     308:  e5912000  ldr r2, [r1]
     30c:  e3c220ff  bic r2, r2, #255 ; 0xff
     310:  e3c22cff  bic r2, r2, #65280 ; 0xff00
     314:  e3c228ff  bic r2, r2, #16711680 ; 0xff0000
     318:  e3c2247f  bic r2, r2, #2130706432 ; 0x7f000000
     31c:  e5812000  str r2, [r1]
; SRAM_CTRL_REG1 = BIT(24) | BIT(0)
     320:  e59f10fc  ldr r1, [pc, #252] ; 424
     324:  e3a02401  mov r2, #16777216 ; 0x1000000
     328:  e1822003  orr r2, r2, r3
     32c:  e5812000  str r2, [r1]
...
     420:  .word 0300169c
     424:  .word 03000004

Then U-Boot SPL[1] sets the SRAM back to "normal mode" before turning
off the VE gating and reset:

	//VE SRAM:set sram to normal mode, default boot mode
	reg_val = readl(SUNXI_SYSCRL_BASE+0X0004);
	reg_val &= ~(0x1<<24);
	writel(reg_val, SUNXI_SYSCRL_BASE+0X0004);

	//VE gating&VE Bus Reset :brom set them, but not require now
	reg_val = readl(CCMU_VE_BGR_REG);
	reg_val &= ~(0x1<<0);
	reg_val &= ~(0x1<<16);
	writel(reg_val, CCMU_VE_BGR_REG);

Other SoCs have a similar code to unmap SRAM C[2]. The AHB1 bus clock
frequency limitation makes sense given that it has to go through the VE
hardware block to get to the SRAM.

In fact, the AHB1 clock limitation when using the low mapping should be
reason enough to prefer the high mapping.

Cheers,
Samuel

[1]:
https://github.com/Allwinner-Homlet/H6-BSP4.9-brandy/blob/master/u-boot-2014.07/board/sunxi/sun50iw6p1/sun50iw6p1.c#L60
[2]:
https://github.com/Allwinner-Homlet/H6-BSP4.9-brandy/blob/master/u-boot-2014.07/board/sunxi/sun8iw10p1/sun8iw10p1.c#L75

>> ---
>> diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i-v3s.dtsi
>> index e8f304125e2d..90d703e5b73b 100644
>> --- a/arch/arm/boot/dts/sun8i-v3s.dtsi
>> +++ b/arch/arm/boot/dts/sun8i-v3s.dtsi
>> @@ -162,17 +162,17 @@ syscon: system-control@1c00000 {
>>                         #size-cells = <1>;
>>                         ranges;
>>
>> -                       sram_c: sram@1d00000 {
>> +                       sram_c: sram@4000 {
>>                                 compatible = "mmio-sram";
>> -                               reg = <0x01d00000 0x80000>;
>> +                               reg = <0x4000 0xb000>;
>>                                 #address-cells = <1>;
>>                                 #size-cells = <1>;
>> -                               ranges = <0 0x01d00000 0x80000>;
>> +                               ranges = <0 0 0x4000 0xb000>;
>>
>>                                 ve_sram: sram-section@0 {
>>                                         compatible = "allwinner,sun8i-v3s-sram-c1",
>>                                                      "allwinner,sun4i-a10-sram-c1";
>> -                                       reg = <0x000000 0x80000>;
>> +                                       reg = <0x0 0xb000>;
>>                                 };
>>                         };
>>                 };
>> ---
>>
>> Does someone have accessible specific documentation of VE/cedrus for V3s ?
> 
> I doubt such information exists.
> 
> 
> Regards
> ChenYu
> 
>> Regards, Martin
>>
>>> ChenYu
>>>
>>>> +                               #address-cells = <1>;
>>>> +                               #size-cells = <1>;
>>>> +                               ranges = <0 0x01d00000 0x80000>;
>>>> +
>>>> +                               ve_sram: sram-section@0 {
>>>> +                                       compatible = "allwinner,sun8i-v3s-sram-c1",
>>>> +                                                    "allwinner,sun4i-a10-sram-c1";
>>>> +                                       reg = <0x000000 0x80000>;
>>>> +                               };
>>>> +                       };
>>>>                 };
>>>>
>>>>                 tcon0: lcd-controller@1c0c000 {
>>>> --
>>>> 2.25.1
>>>>
>>>>
>>>> _______________________________________________
>>>> linux-arm-kernel mailing list
>>>> linux-arm-kernel@lists.infradead.org
>>>> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>>>
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>