From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755508AbdETBjF convert rfc822-to-8bit (ORCPT ); Fri, 19 May 2017 21:39:05 -0400 Received: from smtp.csie.ntu.edu.tw ([140.112.30.61]:34070 "EHLO smtp.csie.ntu.edu.tw" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755189AbdETBjD (ORCPT ); Fri, 19 May 2017 21:39:03 -0400 MIME-Version: 1.0 In-Reply-To: <1958057.WDKm0nQKgW@jernej-laptop> References: <20170517164354.16399-1-icenowy@aosc.io> <20170519180330.7hpfkdqk3r2x3kn5@flea.home> <3FCDBC05-20A1-460C-A21B-8C3E9C776768@aosc.io> <1958057.WDKm0nQKgW@jernej-laptop> From: Chen-Yu Tsai Date: Sat, 20 May 2017 09:37:53 +0800 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [linux-sunxi] Re: [RFC PATCH 07/11] drm: sun4i: add support for the TV encoder in H3 SoC To: =?UTF-8?Q?Jernej_=C5=A0krabec?= Cc: linux-sunxi , Icenowy Zheng , Maxime Ripard , Rob Herring , Chen-Yu Tsai , dri-devel , devicetree , linux-arm-kernel , linux-kernel , linux-clk Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8BIT Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Sat, May 20, 2017 at 2:23 AM, Jernej Škrabec wrote: > Hi, > > Dne petek, 19. maj 2017 ob 20:08:18 CEST je Icenowy Zheng napisal(a): >> 于 2017年5月20日 GMT+08:00 上午2:03:30, Maxime Ripard electrons.com> 写到: >> >On Thu, May 18, 2017 at 12:43:50AM +0800, Icenowy Zheng wrote: >> >> Allwinner H3 features a TV encoder similar to the one in earlier >> > >> >SoCs, >> > >> >> but with some different points about clocks: >> >> - It has a mod clock and a bus clock. >> >> - The mod clock must be at a fixed rate to generate signal. >> > >> >Why? >> >> It's experiment result by Jernej. >> >> The clock rates in BSP kernel is also specially designed >> (PLL_DE at 432MHz) in order to be able to feed the TVE. > > My experiments and search through BSP code showed that TVE seems to have > additional fixed predivider 8. So if you want to generate 27 MHz clock, unit > has to be feed with 216 MHz. > > TVE has only one PLL source PLL_DE. And since 216 MHz is a bit low for DE2, > BSP defaults to 432 MHz for PLL_DE and use divider 2 to generate 216 MHz. This > clock is then divided by 8 internaly to get final 27 MHz. > > Please note that I don't have any hard evidence to support that, only > experimental data. However, only that explanation make sense to me. > > BTW, BSP H3/H5 TV driver supports only PAL and NTSC which both use 27 MHz base > clock. Further experiments are needed to check if there is any possibility to > have other resolutions by manipulating clocks and give other proper settings. > I plan to do that, but not in very near future. You only have composite video output, and those are the only 2 standard resolutions that make any sense. ChenYu