[PATCH 0/3] ARM: dts: sun8i: r40: fix SPI address and reorder nodes

[PATCH 0/3] ARM: dts: sun8i: r40: fix SPI address and reorder nodes

[Chen-Yu Tsai]

From: Chen-Yu Tsai <wens@csie.org>

Hi,

Here are some fixes for the R40 device tree for v5.6. The base addresses
for SPI2 and SPI3 were incorrect and are fixed. I also found some nodes
were not added in the proper order, possibly because git matched the
incorrect place when applying the patch. These are fixed as well.

ChenYu

Chen-Yu Tsai (3):
  ARM: dts: sun8i: r40: Move AHCI device node based on address order
  ARM: dts: sun8i: r40: Fix register base address for SPI2 and SPI3
  ARM: dts: sun8i: r40: Move SPI device nodes based on address order

 arch/arm/boot/dts/sun8i-r40.dtsi | 126 +++++++++++++++----------------
 1 file changed, 63 insertions(+), 63 deletions(-)

-- 
2.25.1

[PATCH 1/3] ARM: dts: sun8i: r40: Move AHCI device node based on address order

[Chen-Yu Tsai]

From: Chen-Yu Tsai <wens@csie.org>

When the AHCI device node was added, it was added in the wrong location
in the device tree file. The device nodes should be sorted by register
address.

Move the device node to before EHCI1, where it belongs.

Fixes: 41c64d3318aa ("ARM: dts: sun8i: r40: add sata node")
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
 arch/arm/boot/dts/sun8i-r40.dtsi | 22 +++++++++++-----------
 1 file changed, 11 insertions(+), 11 deletions(-)

diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi
index d5442b5b6fd2..b278686d0c22 100644
--- a/arch/arm/boot/dts/sun8i-r40.dtsi
+++ b/arch/arm/boot/dts/sun8i-r40.dtsi
@@ -307,6 +307,17 @@ crypto: crypto@1c15000 {
 			resets = <&ccu RST_BUS_CE>;
 		};
 
+		ahci: sata@1c18000 {
+			compatible = "allwinner,sun8i-r40-ahci";
+			reg = <0x01c18000 0x1000>;
+			interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_BUS_SATA>, <&ccu CLK_SATA>;
+			resets = <&ccu RST_BUS_SATA>;
+			reset-names = "ahci";
+			status = "disabled";
+
+		};
+
 		ehci1: usb@1c19000 {
 			compatible = "allwinner,sun8i-r40-ehci", "generic-ehci";
 			reg = <0x01c19000 0x100>;
@@ -733,17 +744,6 @@ spi3: spi@1c0f000 {
 			#size-cells = <0>;
 		};
 
-		ahci: sata@1c18000 {
-			compatible = "allwinner,sun8i-r40-ahci";
-			reg = <0x01c18000 0x1000>;
-			interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&ccu CLK_BUS_SATA>, <&ccu CLK_SATA>;
-			resets = <&ccu RST_BUS_SATA>;
-			reset-names = "ahci";
-			status = "disabled";
-
-		};
-
 		gmac: ethernet@1c50000 {
 			compatible = "allwinner,sun8i-r40-gmac";
 			syscon = <&ccu>;
-- 
2.25.1

[PATCH 2/3] ARM: dts: sun8i: r40: Fix register base address for SPI2 and SPI3

[Chen-Yu Tsai]

From: Chen-Yu Tsai <wens@csie.org>

When the SPI device nodes were added, SPI2 and SPI3 had incorrect
register base addresses.

Fix the base address for both of them.

Fixes: 554581b79139 ("ARM: dts: sun8i: R40: Add SPI controllers nodes and pinmuxes")
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
 arch/arm/boot/dts/sun8i-r40.dtsi | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi
index b278686d0c22..81cc92ddc78b 100644
--- a/arch/arm/boot/dts/sun8i-r40.dtsi
+++ b/arch/arm/boot/dts/sun8i-r40.dtsi
@@ -718,10 +718,10 @@ spi1: spi@1c06000 {
 			#size-cells = <0>;
 		};
 
-		spi2: spi@1c07000 {
+		spi2: spi@1c17000 {
 			compatible = "allwinner,sun8i-r40-spi",
 				     "allwinner,sun8i-h3-spi";
-			reg = <0x01c07000 0x1000>;
+			reg = <0x01c17000 0x1000>;
 			interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&ccu CLK_BUS_SPI2>, <&ccu CLK_SPI2>;
 			clock-names = "ahb", "mod";
@@ -731,10 +731,10 @@ spi2: spi@1c07000 {
 			#size-cells = <0>;
 		};
 
-		spi3: spi@1c0f000 {
+		spi3: spi@1c1f000 {
 			compatible = "allwinner,sun8i-r40-spi",
 				     "allwinner,sun8i-h3-spi";
-			reg = <0x01c0f000 0x1000>;
+			reg = <0x01c1f000 0x1000>;
 			interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&ccu CLK_BUS_SPI3>, <&ccu CLK_SPI3>;
 			clock-names = "ahb", "mod";
-- 
2.25.1

[PATCH 3/3] ARM: dts: sun8i: r40: Move SPI device nodes based on address order

[Chen-Yu Tsai]

From: Chen-Yu Tsai <wens@csie.org>

When the SPI device nodes were added, they were added in the wrong
location in the device tree file. The device nodes should be sorted
by register address.

Move the devices node to their correct positions within the file.

Fixes: 554581b79139 ("ARM: dts: sun8i: R40: Add SPI controllers nodes and pinmuxes")
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
 arch/arm/boot/dts/sun8i-r40.dtsi | 104 +++++++++++++++----------------
 1 file changed, 52 insertions(+), 52 deletions(-)

diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi
index 81cc92ddc78b..f0ede4f52aa3 100644
--- a/arch/arm/boot/dts/sun8i-r40.dtsi
+++ b/arch/arm/boot/dts/sun8i-r40.dtsi
@@ -198,6 +198,32 @@ nmi_intc: interrupt-controller@1c00030 {
 			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
 		};
 
+		spi0: spi@1c05000 {
+			compatible = "allwinner,sun8i-r40-spi",
+				     "allwinner,sun8i-h3-spi";
+			reg = <0x01c05000 0x1000>;
+			interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
+			clock-names = "ahb", "mod";
+			resets = <&ccu RST_BUS_SPI0>;
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		spi1: spi@1c06000 {
+			compatible = "allwinner,sun8i-r40-spi",
+				     "allwinner,sun8i-h3-spi";
+			reg = <0x01c06000 0x1000>;
+			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
+			clock-names = "ahb", "mod";
+			resets = <&ccu RST_BUS_SPI1>;
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
 		csi0: csi@1c09000 {
 			compatible = "allwinner,sun8i-r40-csi0",
 				     "allwinner,sun7i-a20-csi0";
@@ -307,6 +333,19 @@ crypto: crypto@1c15000 {
 			resets = <&ccu RST_BUS_CE>;
 		};
 
+		spi2: spi@1c17000 {
+			compatible = "allwinner,sun8i-r40-spi",
+				     "allwinner,sun8i-h3-spi";
+			reg = <0x01c17000 0x1000>;
+			interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_BUS_SPI2>, <&ccu CLK_SPI2>;
+			clock-names = "ahb", "mod";
+			resets = <&ccu RST_BUS_SPI2>;
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
 		ahci: sata@1c18000 {
 			compatible = "allwinner,sun8i-r40-ahci";
 			reg = <0x01c18000 0x1000>;
@@ -364,6 +403,19 @@ ohci2: usb@1c1c400 {
 			status = "disabled";
 		};
 
+		spi3: spi@1c1f000 {
+			compatible = "allwinner,sun8i-r40-spi",
+				     "allwinner,sun8i-h3-spi";
+			reg = <0x01c1f000 0x1000>;
+			interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_BUS_SPI3>, <&ccu CLK_SPI3>;
+			clock-names = "ahb", "mod";
+			resets = <&ccu RST_BUS_SPI3>;
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
 		ccu: clock@1c20000 {
 			compatible = "allwinner,sun8i-r40-ccu";
 			reg = <0x01c20000 0x400>;
@@ -692,58 +744,6 @@ i2c4: i2c@1c2c000 {
 			#size-cells = <0>;
 		};
 
-		spi0: spi@1c05000 {
-			compatible = "allwinner,sun8i-r40-spi",
-				     "allwinner,sun8i-h3-spi";
-			reg = <0x01c05000 0x1000>;
-			interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
-			clock-names = "ahb", "mod";
-			resets = <&ccu RST_BUS_SPI0>;
-			status = "disabled";
-			#address-cells = <1>;
-			#size-cells = <0>;
-		};
-
-		spi1: spi@1c06000 {
-			compatible = "allwinner,sun8i-r40-spi",
-				     "allwinner,sun8i-h3-spi";
-			reg = <0x01c06000 0x1000>;
-			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
-			clock-names = "ahb", "mod";
-			resets = <&ccu RST_BUS_SPI1>;
-			status = "disabled";
-			#address-cells = <1>;
-			#size-cells = <0>;
-		};
-
-		spi2: spi@1c17000 {
-			compatible = "allwinner,sun8i-r40-spi",
-				     "allwinner,sun8i-h3-spi";
-			reg = <0x01c17000 0x1000>;
-			interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&ccu CLK_BUS_SPI2>, <&ccu CLK_SPI2>;
-			clock-names = "ahb", "mod";
-			resets = <&ccu RST_BUS_SPI2>;
-			status = "disabled";
-			#address-cells = <1>;
-			#size-cells = <0>;
-		};
-
-		spi3: spi@1c1f000 {
-			compatible = "allwinner,sun8i-r40-spi",
-				     "allwinner,sun8i-h3-spi";
-			reg = <0x01c1f000 0x1000>;
-			interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&ccu CLK_BUS_SPI3>, <&ccu CLK_SPI3>;
-			clock-names = "ahb", "mod";
-			resets = <&ccu RST_BUS_SPI3>;
-			status = "disabled";
-			#address-cells = <1>;
-			#size-cells = <0>;
-		};
-
 		gmac: ethernet@1c50000 {
 			compatible = "allwinner,sun8i-r40-gmac";
 			syscon = <&ccu>;
-- 
2.25.1

Re: [PATCH 0/3] ARM: dts: sun8i: r40: fix SPI address and reorder nodes

[Maxime Ripard]

On Wed, Mar 11, 2020 at 01:47:06AM +0800, Chen-Yu Tsai wrote:
> From: Chen-Yu Tsai <wens@csie.org>
>
> Hi,
>
> Here are some fixes for the R40 device tree for v5.6. The base addresses
> for SPI2 and SPI3 were incorrect and are fixed. I also found some nodes
> were not added in the proper order, possibly because git matched the
> incorrect place when applying the patch. These are fixed as well.
>
> ChenYu

Acked-by: Maxime Ripard <mripard@kernel.org>

Thanks!
Maxime

Re: [PATCH 1/3] ARM: dts: sun8i: r40: Move AHCI device node based on address order

[Andre Przywara]

On Wed, 11 Mar 2020 01:47:07 +0800
Chen-Yu Tsai <wens@kernel.org> wrote:

> From: Chen-Yu Tsai <wens@csie.org>
> 
> When the AHCI device node was added, it was added in the wrong location
> in the device tree file. The device nodes should be sorted by register
> address.
> 
> Move the device node to before EHCI1, where it belongs.
> 
> Fixes: 41c64d3318aa ("ARM: dts: sun8i: r40: add sata node")
> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
> ---
>  arch/arm/boot/dts/sun8i-r40.dtsi | 22 +++++++++++-----------
>  1 file changed, 11 insertions(+), 11 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi
> index d5442b5b6fd2..b278686d0c22 100644
> --- a/arch/arm/boot/dts/sun8i-r40.dtsi
> +++ b/arch/arm/boot/dts/sun8i-r40.dtsi
> @@ -307,6 +307,17 @@ crypto: crypto@1c15000 {
>  			resets = <&ccu RST_BUS_CE>;
>  		};
>  
> +		ahci: sata@1c18000 {
> +			compatible = "allwinner,sun8i-r40-ahci";
> +			reg = <0x01c18000 0x1000>;
> +			interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&ccu CLK_BUS_SATA>, <&ccu CLK_SATA>;
> +			resets = <&ccu RST_BUS_SATA>;
> +			reset-names = "ahci";
> +			status = "disabled";
> +

Did this empty line serve any particular purpose before? If not, you could remove it on the way.

With that fixed:

Reviewed-by: Andre Przywara <andre.przywara@arm.com>

Thanks,
Andre.

> +		};
> +
>  		ehci1: usb@1c19000 {
>  			compatible = "allwinner,sun8i-r40-ehci", "generic-ehci";
>  			reg = <0x01c19000 0x100>;
> @@ -733,17 +744,6 @@ spi3: spi@1c0f000 {
>  			#size-cells = <0>;
>  		};
>  
> -		ahci: sata@1c18000 {
> -			compatible = "allwinner,sun8i-r40-ahci";
> -			reg = <0x01c18000 0x1000>;
> -			interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
> -			clocks = <&ccu CLK_BUS_SATA>, <&ccu CLK_SATA>;
> -			resets = <&ccu RST_BUS_SATA>;
> -			reset-names = "ahci";
> -			status = "disabled";
> -
> -		};
> -
>  		gmac: ethernet@1c50000 {
>  			compatible = "allwinner,sun8i-r40-gmac";
>  			syscon = <&ccu>;

Re: [PATCH 2/3] ARM: dts: sun8i: r40: Fix register base address for SPI2 and SPI3

[Andre Przywara]

On Wed, 11 Mar 2020 01:47:08 +0800
Chen-Yu Tsai <wens@kernel.org> wrote:

Hi Chen-Yu,

sorry, didn't spot this before posting my version!

> From: Chen-Yu Tsai <wens@csie.org>
> 
> When the SPI device nodes were added, SPI2 and SPI3 had incorrect
> register base addresses.
> 
> Fix the base address for both of them.
> 
> Fixes: 554581b79139 ("ARM: dts: sun8i: R40: Add SPI controllers nodes and pinmuxes")
> Signed-off-by: Chen-Yu Tsai <wens@csie.org>

Reviewed-by: Andre Przywara <andre.przywara@arm.com>

As you suggested, it would be nice to add Juan's reported by, since he reported this before:
https://groups.google.com/forum/#!topic/linux-sunxi/5ZzkDXx2F-M

Cheers,
Andre

> ---
>  arch/arm/boot/dts/sun8i-r40.dtsi | 8 ++++----
>  1 file changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi
> index b278686d0c22..81cc92ddc78b 100644
> --- a/arch/arm/boot/dts/sun8i-r40.dtsi
> +++ b/arch/arm/boot/dts/sun8i-r40.dtsi
> @@ -718,10 +718,10 @@ spi1: spi@1c06000 {
>  			#size-cells = <0>;
>  		};
>  
> -		spi2: spi@1c07000 {
> +		spi2: spi@1c17000 {
>  			compatible = "allwinner,sun8i-r40-spi",
>  				     "allwinner,sun8i-h3-spi";
> -			reg = <0x01c07000 0x1000>;
> +			reg = <0x01c17000 0x1000>;
>  			interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
>  			clocks = <&ccu CLK_BUS_SPI2>, <&ccu CLK_SPI2>;
>  			clock-names = "ahb", "mod";
> @@ -731,10 +731,10 @@ spi2: spi@1c07000 {
>  			#size-cells = <0>;
>  		};
>  
> -		spi3: spi@1c0f000 {
> +		spi3: spi@1c1f000 {
>  			compatible = "allwinner,sun8i-r40-spi",
>  				     "allwinner,sun8i-h3-spi";
> -			reg = <0x01c0f000 0x1000>;
> +			reg = <0x01c1f000 0x1000>;
>  			interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
>  			clocks = <&ccu CLK_BUS_SPI3>, <&ccu CLK_SPI3>;
>  			clock-names = "ahb", "mod";

Re: [PATCH 3/3] ARM: dts: sun8i: r40: Move SPI device nodes based on address order

[Andre Przywara]

On Wed, 11 Mar 2020 01:47:09 +0800
Chen-Yu Tsai <wens@kernel.org> wrote:

> From: Chen-Yu Tsai <wens@csie.org>
> 
> When the SPI device nodes were added, they were added in the wrong
> location in the device tree file. The device nodes should be sorted
> by register address.
> 
> Move the devices node to their correct positions within the file.

Diffed the minus and plus lines, it's indeed a pure move:

Reviewed-by: Andre Przywara <andre.przywara@arm.com>

Cheers,
Andre

> 
> Fixes: 554581b79139 ("ARM: dts: sun8i: R40: Add SPI controllers nodes and pinmuxes")
> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
> ---
>  arch/arm/boot/dts/sun8i-r40.dtsi | 104 +++++++++++++++----------------
>  1 file changed, 52 insertions(+), 52 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi
> index 81cc92ddc78b..f0ede4f52aa3 100644
> --- a/arch/arm/boot/dts/sun8i-r40.dtsi
> +++ b/arch/arm/boot/dts/sun8i-r40.dtsi
> @@ -198,6 +198,32 @@ nmi_intc: interrupt-controller@1c00030 {
>  			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
>  		};
>  
> +		spi0: spi@1c05000 {
> +			compatible = "allwinner,sun8i-r40-spi",
> +				     "allwinner,sun8i-h3-spi";
> +			reg = <0x01c05000 0x1000>;
> +			interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
> +			clock-names = "ahb", "mod";
> +			resets = <&ccu RST_BUS_SPI0>;
> +			status = "disabled";
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +		};
> +
> +		spi1: spi@1c06000 {
> +			compatible = "allwinner,sun8i-r40-spi",
> +				     "allwinner,sun8i-h3-spi";
> +			reg = <0x01c06000 0x1000>;
> +			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
> +			clock-names = "ahb", "mod";
> +			resets = <&ccu RST_BUS_SPI1>;
> +			status = "disabled";
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +		};
> +
>  		csi0: csi@1c09000 {
>  			compatible = "allwinner,sun8i-r40-csi0",
>  				     "allwinner,sun7i-a20-csi0";
> @@ -307,6 +333,19 @@ crypto: crypto@1c15000 {
>  			resets = <&ccu RST_BUS_CE>;
>  		};
>  
> +		spi2: spi@1c17000 {
> +			compatible = "allwinner,sun8i-r40-spi",
> +				     "allwinner,sun8i-h3-spi";
> +			reg = <0x01c17000 0x1000>;
> +			interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&ccu CLK_BUS_SPI2>, <&ccu CLK_SPI2>;
> +			clock-names = "ahb", "mod";
> +			resets = <&ccu RST_BUS_SPI2>;
> +			status = "disabled";
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +		};
> +
>  		ahci: sata@1c18000 {
>  			compatible = "allwinner,sun8i-r40-ahci";
>  			reg = <0x01c18000 0x1000>;
> @@ -364,6 +403,19 @@ ohci2: usb@1c1c400 {
>  			status = "disabled";
>  		};
>  
> +		spi3: spi@1c1f000 {
> +			compatible = "allwinner,sun8i-r40-spi",
> +				     "allwinner,sun8i-h3-spi";
> +			reg = <0x01c1f000 0x1000>;
> +			interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&ccu CLK_BUS_SPI3>, <&ccu CLK_SPI3>;
> +			clock-names = "ahb", "mod";
> +			resets = <&ccu RST_BUS_SPI3>;
> +			status = "disabled";
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +		};
> +
>  		ccu: clock@1c20000 {
>  			compatible = "allwinner,sun8i-r40-ccu";
>  			reg = <0x01c20000 0x400>;
> @@ -692,58 +744,6 @@ i2c4: i2c@1c2c000 {
>  			#size-cells = <0>;
>  		};
>  
> -		spi0: spi@1c05000 {
> -			compatible = "allwinner,sun8i-r40-spi",
> -				     "allwinner,sun8i-h3-spi";
> -			reg = <0x01c05000 0x1000>;
> -			interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
> -			clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
> -			clock-names = "ahb", "mod";
> -			resets = <&ccu RST_BUS_SPI0>;
> -			status = "disabled";
> -			#address-cells = <1>;
> -			#size-cells = <0>;
> -		};
> -
> -		spi1: spi@1c06000 {
> -			compatible = "allwinner,sun8i-r40-spi",
> -				     "allwinner,sun8i-h3-spi";
> -			reg = <0x01c06000 0x1000>;
> -			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
> -			clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
> -			clock-names = "ahb", "mod";
> -			resets = <&ccu RST_BUS_SPI1>;
> -			status = "disabled";
> -			#address-cells = <1>;
> -			#size-cells = <0>;
> -		};
> -
> -		spi2: spi@1c17000 {
> -			compatible = "allwinner,sun8i-r40-spi",
> -				     "allwinner,sun8i-h3-spi";
> -			reg = <0x01c17000 0x1000>;
> -			interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
> -			clocks = <&ccu CLK_BUS_SPI2>, <&ccu CLK_SPI2>;
> -			clock-names = "ahb", "mod";
> -			resets = <&ccu RST_BUS_SPI2>;
> -			status = "disabled";
> -			#address-cells = <1>;
> -			#size-cells = <0>;
> -		};
> -
> -		spi3: spi@1c1f000 {
> -			compatible = "allwinner,sun8i-r40-spi",
> -				     "allwinner,sun8i-h3-spi";
> -			reg = <0x01c1f000 0x1000>;
> -			interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
> -			clocks = <&ccu CLK_BUS_SPI3>, <&ccu CLK_SPI3>;
> -			clock-names = "ahb", "mod";
> -			resets = <&ccu RST_BUS_SPI3>;
> -			status = "disabled";
> -			#address-cells = <1>;
> -			#size-cells = <0>;
> -		};
> -
>  		gmac: ethernet@1c50000 {
>  			compatible = "allwinner,sun8i-r40-gmac";
>  			syscon = <&ccu>;

Re: [PATCH 1/3] ARM: dts: sun8i: r40: Move AHCI device node based on address order

[Chen-Yu Tsai]

On Wed, Mar 11, 2020 at 6:59 PM Andre Przywara <andre.przywara@arm.com> wrote:
>
> On Wed, 11 Mar 2020 01:47:07 +0800
> Chen-Yu Tsai <wens@kernel.org> wrote:
>
> > From: Chen-Yu Tsai <wens@csie.org>
> >
> > When the AHCI device node was added, it was added in the wrong location
> > in the device tree file. The device nodes should be sorted by register
> > address.
> >
> > Move the device node to before EHCI1, where it belongs.
> >
> > Fixes: 41c64d3318aa ("ARM: dts: sun8i: r40: add sata node")
> > Signed-off-by: Chen-Yu Tsai <wens@csie.org>
> > ---
> >  arch/arm/boot/dts/sun8i-r40.dtsi | 22 +++++++++++-----------
> >  1 file changed, 11 insertions(+), 11 deletions(-)
> >
> > diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi
> > index d5442b5b6fd2..b278686d0c22 100644
> > --- a/arch/arm/boot/dts/sun8i-r40.dtsi
> > +++ b/arch/arm/boot/dts/sun8i-r40.dtsi
> > @@ -307,6 +307,17 @@ crypto: crypto@1c15000 {
> >                       resets = <&ccu RST_BUS_CE>;
> >               };
> >
> > +             ahci: sata@1c18000 {
> > +                     compatible = "allwinner,sun8i-r40-ahci";
> > +                     reg = <0x01c18000 0x1000>;
> > +                     interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
> > +                     clocks = <&ccu CLK_BUS_SATA>, <&ccu CLK_SATA>;
> > +                     resets = <&ccu RST_BUS_SATA>;
> > +                     reset-names = "ahci";
> > +                     status = "disabled";
> > +
>
> Did this empty line serve any particular purpose before? If not, you could remove it on the way.

Can't say there is. Removed when applied.

> With that fixed:
>
> Reviewed-by: Andre Przywara <andre.przywara@arm.com>
>
> Thanks,
> Andre.

Thanks
ChenYu

> > +             };
> > +
> >               ehci1: usb@1c19000 {
> >                       compatible = "allwinner,sun8i-r40-ehci", "generic-ehci";
> >                       reg = <0x01c19000 0x100>;
> > @@ -733,17 +744,6 @@ spi3: spi@1c0f000 {
> >                       #size-cells = <0>;
> >               };
> >
> > -             ahci: sata@1c18000 {
> > -                     compatible = "allwinner,sun8i-r40-ahci";
> > -                     reg = <0x01c18000 0x1000>;
> > -                     interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
> > -                     clocks = <&ccu CLK_BUS_SATA>, <&ccu CLK_SATA>;
> > -                     resets = <&ccu RST_BUS_SATA>;
> > -                     reset-names = "ahci";
> > -                     status = "disabled";
> > -
> > -             };
> > -
> >               gmac: ethernet@1c50000 {
> >                       compatible = "allwinner,sun8i-r40-gmac";
> >                       syscon = <&ccu>;
>

Re: [PATCH 0/3] ARM: dts: sun8i: r40: fix SPI address and reorder nodes

[Chen-Yu Tsai]

On Wed, Mar 11, 2020 at 2:10 AM Maxime Ripard <maxime@cerno.tech> wrote:
>
> On Wed, Mar 11, 2020 at 01:47:06AM +0800, Chen-Yu Tsai wrote:
> > From: Chen-Yu Tsai <wens@csie.org>
> >
> > Hi,
> >
> > Here are some fixes for the R40 device tree for v5.6. The base addresses
> > for SPI2 and SPI3 were incorrect and are fixed. I also found some nodes
> > were not added in the proper order, possibly because git matched the
> > incorrect place when applying the patch. These are fixed as well.
> >
> > ChenYu
>
> Acked-by: Maxime Ripard <mripard@kernel.org>

Merged all three for v5.6 with Andre's Reviewed-by and a reported-by
for the SPI address base patch.