From: Chen-Yu Tsai <wens@csie.org>
To: Priit Laes <plaes@plaes.org>
Cc: Maxime Ripard <maxime.ripard@free-electrons.com>,
linux-kernel <linux-kernel@vger.kernel.org>,
linux-arm-kernel <linux-arm-kernel@lists.infradead.org>,
devicetree <devicetree@vger.kernel.org>,
linux-clk <linux-clk@vger.kernel.org>,
linux-sunxi <linux-sunxi@googlegroups.com>,
Icenowy Zheng <icenowy@aosc.xyz>,
Russell King <linux@armlinux.org.uk>,
Chen-Yu Tsai <wens@csie.org>, Mark Rutland <mark.rutland@arm.com>,
Rob Herring <robh+dt@kernel.org>,
Stephen Boyd <sboyd@codeaurora.org>,
Michael Turquette <mturquette@baylibre.com>,
Philipp Zabel <p.zabel@pengutronix.de>
Subject: Re: [linux-sunxi] Re: [PATCH v2 1/6] clk: sunxi-ng: Add sun4i/sun7i CCU driver
Date: Fri, 21 Apr 2017 09:46:58 +0800 [thread overview]
Message-ID: <CAGb2v66iNddKty4ObeGuVRDOp1NV-9A6=cg7omGMiDLJe7T_=g@mail.gmail.com> (raw)
In-Reply-To: <20170420195917.GA16113@plaes.org>
On Fri, Apr 21, 2017 at 3:59 AM, Priit Laes <plaes@plaes.org> wrote:
> On Fri, Apr 07, 2017 at 03:38:05PM +0200, Maxime Ripard wrote:
>> Hi Priit,
>>
>> On Tue, Apr 04, 2017 at 08:09:19PM +0000, Priit Laes wrote:
>> > > > +/* Not documented on A10 */
>> > > > +static SUNXI_CCU_GATE(pll_periph_sata_clk, "pll-periph-sata", "pll-periph",
>> > > > + 0x028, BIT(14), 0);
>> > >
>> > > The rate doesn't come from pll-periph directly, does it?
>> >
>> > So it uses hosc (24MHz parent clock) instead of pll-periph?
>>
>> I never looked too much at this, but it looks more like the input is
>> pll-periph-sata itself.
>
> OK, I think I have now fixed most of the issues thanks to Maxime and Chen-Yu
> and I'm almost ready to send out V3.
>
> From my side there is only single issue remaining - how to create "sata-ext"
> clock?
>
> [snip]
> static struct ccu_div pll_periph_sata_clk = {
> .enable = BIT(14),
> .div = _SUNXI_CCU_DIV(0, 2),
> .common = {
> .prediv = 6,
> .reg = 0x028,
> .features = CCU_FEATURE_ALL_PREDIV,
> .hw.init = CLK_HW_INIT("pll-periph-sata",
> "pll-periph-base",
> &ccu_nk_ops, 0),
> },
> };
>
> static const char* const sata_parents[] = {"pll-periph-sata", "sata-ext"};
> static SUNXI_CCU_MUX_WITH_GATE(sata_clk, "sata", sata_parents,
> 0x0c8, 24, 1, BIT(31), 0);
> [/snip]
>
> Should I create a fixed-clock node in the dtsi:
>
> sata-ext: clk@0 {
> #clock-cells = <0>;
> compatible = "fixed-clock";
> clock-frequency = <200000000>;
> clock-output-names = "sata-ext";
> };
You can just leave it missing. You probably shouldn't register it
if it's not populated. The clk core can cope with missing parents,
as long as they aren't all missing.
>
> And would it also need pio definition?
Nope. It has dedicated pins.
ChenYu
next prev parent reply other threads:[~2017-04-21 1:47 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-03-26 17:20 [PATCH v2 0/6] ARM: sunxi: Convert sun4i/sun7i series SoCs to sunxi-ng Priit Laes
2017-03-26 17:20 ` [PATCH v2 1/6] clk: sunxi-ng: Add sun4i/sun7i CCU driver Priit Laes
2017-03-27 7:54 ` Maxime Ripard
2017-04-04 20:09 ` [linux-sunxi] " Priit Laes
2017-04-07 13:38 ` Maxime Ripard
2017-04-20 19:59 ` Priit Laes
2017-04-21 1:46 ` Chen-Yu Tsai [this message]
2017-04-22 12:33 ` [linux-sunxi] " Jonathan Liu
2017-04-22 14:46 ` Jonathan Liu
2017-03-26 17:20 ` [PATCH v2 2/6] ARM: sun7i: Convert to CCU Priit Laes
2017-03-26 17:20 ` [PATCH v2 3/6] ARM: sun4i: " Priit Laes
2017-12-11 22:22 ` [linux-sunxi] " Kevin Hilman
2017-12-12 6:12 ` Priit Laes
2017-12-12 17:26 ` Priit Laes
2017-12-12 21:24 ` Kevin Hilman
2017-12-13 13:44 ` Maxime Ripard
2017-12-13 17:09 ` Priit Laes
2017-12-13 17:13 ` Priit Laes
2017-12-13 19:46 ` Kevin Hilman
2018-01-05 16:10 ` Kevin Hilman
2018-01-08 9:15 ` Chen-Yu Tsai
2017-03-26 17:20 ` [PATCH v2 4/6] dt-bindings: List devicetree binding for the CCU of Allwinner A20 Priit Laes
2017-03-26 17:20 ` [PATCH v2 5/6] dt-bindings: List devicetree binding for the CCU of Allwinner A10 Priit Laes
2017-03-30 23:19 ` Rob Herring
2017-03-26 17:20 ` [PATCH v2 6/6] clk: sunxi-ng: Display index when clock registration fails Priit Laes
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