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[209.85.167.45]) by smtp.gmail.com with ESMTPSA id z5sm1043966lfe.64.2021.01.27.17.58.04 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 27 Jan 2021 17:58:04 -0800 (PST) Received: by mail-lf1-f45.google.com with SMTP id f1so5522363lfu.3; Wed, 27 Jan 2021 17:58:04 -0800 (PST) X-Received: by 2002:ac2:5293:: with SMTP id q19mr6209580lfm.303.1611799083861; Wed, 27 Jan 2021 17:58:03 -0800 (PST) MIME-Version: 1.0 References: <20210118055040.21910-1-samuel@sholland.org> <161126112131.135928.7664552660827790510.b4-ty@kernel.org> <08e9bc97-c18d-9b8f-28be-3892d77730bf@sholland.org> <20210122104705.bo2x22ef56hdj26q@gilmour> <52b9c9bb-ff75-d1e6-e198-0d388d1c6d73@sholland.org> <20210125105626.fz75dxhi6f7jtcqm@gilmour> In-Reply-To: <20210125105626.fz75dxhi6f7jtcqm@gilmour> From: Chen-Yu Tsai Date: Thu, 28 Jan 2021 09:57:52 +0800 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v5 00/10] sunxi: Support IRQ wakeup from deep sleep To: Samuel Holland , Maxime Ripard Cc: Marc Zyngier , Jernej Skrabec , Thomas Gleixner , Rob Herring , Ondrej Jirman , linux-arm-kernel , linux-kernel , devicetree Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Jan 25, 2021 at 6:56 PM Maxime Ripard wrote: > > On Sat, Jan 23, 2021 at 12:26:26AM -0600, Samuel Holland wrote: > > On 1/22/21 4:47 AM, Maxime Ripard wrote: > > > On Thu, Jan 21, 2021 at 07:33:54PM -0600, Samuel Holland wrote: > > >> On 1/21/21 2:35 PM, Marc Zyngier wrote: > > >>> On Sun, 17 Jan 2021 23:50:30 -0600, Samuel Holland wrote: > > >>>> Allwinner sun6i/sun8i/sun50i SoCs (A31 and newer) have two interrupt > > >>>> controllers: GIC and R_INTC. GIC does not support wakeup. R_INTC handles > > >>>> the external NMI pin, and provides 32+ IRQs to the ARISC. The first 16 > > >>>> of these correspond 1:1 to a block of GIC IRQs starting with the NMI. > > >>>> The last 13-16 multiplex the first (up to) 128 GIC SPIs. > > >>>> > > >>>> This series replaces the existing chained irqchip driver that could only > > >>>> control the NMI, with a stacked irqchip driver that also provides wakeup > > >>>> capability for those multiplexed SPI IRQs. The idea is to preconfigure > > >>>> the ARISC's IRQ controller, and then the ARISC firmware knows to wake up > > >>>> as soon as it receives an IRQ. It can also decide how deep it can > > >>>> suspend based on the enabled wakeup IRQs. > > >>>> > > >>>> [...] > > >>> > > >>> Applied to irq/irqchip-5.12, thanks! > > >>> > > >>> [01/10] dt-bindings: irq: sun6i-r: Split the binding from sun7i-nmi > > >>> commit: ad6b47cdef760410311f41876b21eb0c6fda4717 > > >>> [02/10] dt-bindings: irq: sun6i-r: Add a compatible for the H3 > > >>> commit: 6436eb4417094ea3308b33d8392fc02a1068dc78 > > >>> [03/10] irqchip/sun6i-r: Use a stacked irqchip driver > > >>> commit: 4e34614636b31747b190488240a95647c227021f > > >>> [04/10] irqchip/sun6i-r: Add wakeup support > > >>> commit: 7ab365f6cd6de1e2b0cb1e1e3873dbf68e6f1003 > > >>> > > >>> Please route the dts patches via the soc tree. Also, I had to > > >>> manually fix the first patch as it wouldn't apply on top of > > >>> 5.11-rc4 (which tree has it been diffed against?). Please > > >>> check that the resolution is correct. > > >> > > >> This series was based on sunxi/for-next, which contains commit > > >> 752b0aac99c7 ("dt-bindings: irq: sun7i-nmi: Add binding documentation > > >> for the V3s NMI")[1]. > > > > > > I assume merging the DT bits alone would break things? If so, I guess we > > > can wait for 5.12 to be released before merging it > > > > Patch 5 does not depend on the new driver, so it could be merged at any > > time. Yes, the remaining patches would break things if merged without > > the driver. > > I've applied patch 5 then, could you send the rest of the DT patches > when 5.13-rc1 is out? I've put them in a for-5.13-late branch and merged them into for-next. This should get a bit of boot testing via KernelCI. Maybe we'll get to sending a late pull request for 5.13, maybe not. ChenYu