From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-0.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9E70DC433E3 for ; Wed, 3 Jun 2020 09:49:03 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 86DA920679 for ; Wed, 3 Jun 2020 09:49:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726776AbgFCJtD convert rfc822-to-8bit (ORCPT ); Wed, 3 Jun 2020 05:49:03 -0400 Received: from mail-lf1-f66.google.com ([209.85.167.66]:34297 "EHLO mail-lf1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726099AbgFCJtB (ORCPT ); Wed, 3 Jun 2020 05:49:01 -0400 Received: by mail-lf1-f66.google.com with SMTP id e125so923673lfd.1; Wed, 03 Jun 2020 02:48:59 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=PMOVHnGEcXL7cxNnZJH62mImVMlDJ7z1JOGvnBRid68=; b=Cx7zxwU/XozHp29LQsWwlrR022t3k0/nEIMwP/y+msZSnQSvfFfPQQgoBiKlkdDehC e+T2ITdho5p2bxpH8zvbWRCNh4gRMxqYgL9ooOpM0Cio2B0sog0Oro4lcvLM8mrMuvrr c5KVL55I+lFL19w5YnT2wlnZBNYC7Q32yNHusu2ocO3YiEHulcTLIAyVt/dKi0Y4Wjg7 hw2aNGm9Tiv9zA2Lkv0sTOyn7VMYKrXsSYkHknDORLNNX/k3c9tDhh6l6xvQwpedGpxG jXeIADnJSMid+PPhnLsOLqRxyAREW40zG2jXlNTJi8ootzh4NenajJs7Kx78DuXyGLA7 dIng== X-Gm-Message-State: AOAM533qS9GAtx/twYWxsZW/Jc6chjNpandsbS++5fsbTtlxZ9G1Ya0h 1laBCK2bOjEy3wQdcDXbuklaC0PuxAk= X-Google-Smtp-Source: ABdhPJyyaIyuOWNBAgIVj2qkE/YvtIT3cQ3jw7VMWldMfAnKzXsjU0EcLF1XQ31/gR9QLsXZ2QN1sg== X-Received: by 2002:ac2:5f82:: with SMTP id r2mr1952220lfe.119.1591177738122; Wed, 03 Jun 2020 02:48:58 -0700 (PDT) Received: from mail-lj1-f175.google.com (mail-lj1-f175.google.com. [209.85.208.175]) by smtp.gmail.com with ESMTPSA id l16sm331057lji.138.2020.06.03.02.48.56 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 03 Jun 2020 02:48:57 -0700 (PDT) Received: by mail-lj1-f175.google.com with SMTP id s1so1931460ljo.0; Wed, 03 Jun 2020 02:48:56 -0700 (PDT) X-Received: by 2002:a2e:8047:: with SMTP id p7mr1551215ljg.190.1591177736679; Wed, 03 Jun 2020 02:48:56 -0700 (PDT) MIME-Version: 1.0 References: <20200522030743.10204-1-frank@allwinnertech.com> <20200522030743.10204-2-frank@allwinnertech.com> <20200522151403.7ovbdza2o3cjrb7a@gilmour.lan> In-Reply-To: From: Chen-Yu Tsai Date: Wed, 3 Jun 2020 17:48:44 +0800 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH 1/4] clk: sunxi-ng: add support for the Allwinner A100 CCU To: =?UTF-8?B?5p2O5oms6Z+s?= Cc: Maxime Ripard , "robh+dt" , mturquette , sboyd , "linus.walleij" , "p.zabel" , =?UTF-8?B?6buE54OB55Sf?= , "tiny.windzz" , linux-arm-kernel , devicetree , linux-kernel , linux-clk , linux-gpio Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8BIT Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, Jun 3, 2020 at 5:42 PM 李扬韬 wrote: > > >> + /* Enable the lock bits on all PLLs */ > >> + for (i = 0; i < ARRAY_SIZE(pll_regs); i++) { > >> + val = readl(reg + pll_regs[i]); > >> + val |= BIT(29); > > > >Having a define for that would be nice here > > > >> + writel(val, reg + pll_regs[i]); > >> + } > >> + > >> + /* > >> + * In order to pass the EMI certification, the SDM function of > >> + * the peripheral 1 bus is enabled, and the frequency is still > >> + * calculated using the previous division factor. > >> + */ > >> + writel(0xd1303333, reg + SUN50I_A100_PLL_PERIPH1_PATTERN0_REG); > > > >Same here > > Having a define? I don’t quite understand what you mean, > can you give me an example? What Maxime means is that 0xd1303333 is a magic number. It is better to make a properly named macro, or many macros that you then bitwise-OR together. So you should make macros for each bitfield in that register, which would likely include the SDM calculation factors, the enable bit, and any other fields. ChenYu > MBR, > Yangtao