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[74.125.82.43]) by smtp.gmail.com with ESMTPSA id z70-v6sm2802460ede.6.2018.07.04.01.20.00 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 04 Jul 2018 01:20:00 -0700 (PDT) Received: by mail-wm0-f43.google.com with SMTP id v3-v6so1143490wmh.0 for ; Wed, 04 Jul 2018 01:20:00 -0700 (PDT) X-Received: by 2002:a1c:6fdd:: with SMTP id c90-v6mr902739wmi.16.1530692400382; Wed, 04 Jul 2018 01:20:00 -0700 (PDT) MIME-Version: 1.0 Received: by 2002:adf:a15a:0:0:0:0:0 with HTTP; Wed, 4 Jul 2018 01:19:39 -0700 (PDT) In-Reply-To: <5283f98e-6443-db7a-fe51-6379ed19002c@arm.com> References: <20180511022751.9096-1-samuel@sholland.org> <2c16d5ab-38f7-8f3e-875c-19e8032f440a@arm.com> <5283f98e-6443-db7a-fe51-6379ed19002c@arm.com> From: Chen-Yu Tsai Date: Wed, 4 Jul 2018 16:19:39 +0800 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH 0/2] Allwinner A64 timer workaround To: Marc Zyngier Cc: Samuel Holland , Maxime Ripard , Catalin Marinas , Will Deacon , Daniel Lezcano , Thomas Gleixner , linux-arm-kernel , linux-kernel , linux-sunxi , Mark Rutland Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8BIT Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, Jul 4, 2018 at 4:16 PM, Marc Zyngier wrote: > On 03/07/18 19:42, Samuel Holland wrote: >> On 07/03/18 10:09, Marc Zyngier wrote: >>> On 11/05/18 03:27, Samuel Holland wrote: >>>> Hello, >>>> >>>> Several people (including me) have experienced extremely large system >>>> clock jumps on their A64-based devices, apparently due to the architectural >>>> timer going backward, which is interpreted by Linux as the timer wrapping >>>> around after 2^56 cycles. >>>> >>>> Investigation led to discovery of some obvious problems with this SoC's >>>> architectural timer, and this patch series introduces what I believe is >>>> the simplest workaround. More details are in the commit message for patch >>>> 1. Patch 2 simply enables the workaround in the device tree. >>> >>> What's the deal with this series? There was a couple of nits to address, and >>> I was more or less expecting a v2. >> >> I got reports that people were still occasionally having clock jumps after >> applying this series, so I wanted to attempt a more complete fix, but I haven't >> had time to do any deeper investigation. I think this series is still beneficial >> even if it's not a complete solution, so I'll come back with another patch on >> top of this if/once I get it fully fixed. >> >> I'll prepare a v2 with a bounded loop. Presumably, 3 * (max CPU Hz) / (24MHz >> timer) ≈ 150 should be a conservative iteration limit? > > Should be OK. > > Maxime: How do you want to deal with the documentation aspect? We need > an erratum number, but AFAIU the concept hasn't made it into the silicom > vendor's brain yet. Any chance you could come up with something that > uniquely identifies this? > >> Also, does this make sense to CC to stable? > > Probably not, as the HW never worked, so it is not a regression. A64 support has been in for a few releases now. So while this is not fixing a regression, people will still benefit from it being in stable. ChenYu