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[74.125.82.53]) by smtp.gmail.com with ESMTPSA id o15-v6sm2747990edt.4.2018.06.28.00.00.52 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 28 Jun 2018 00:00:53 -0700 (PDT) Received: by mail-wm0-f53.google.com with SMTP id z13-v6so7787613wma.5; Thu, 28 Jun 2018 00:00:52 -0700 (PDT) X-Received: by 2002:a1c:850c:: with SMTP id h12-v6mr6963261wmd.116.1530169252596; Thu, 28 Jun 2018 00:00:52 -0700 (PDT) MIME-Version: 1.0 Received: by 2002:adf:a15a:0:0:0:0:0 with HTTP; Thu, 28 Jun 2018 00:00:32 -0700 (PDT) In-Reply-To: <1669385.k4L9lni8DF@jernej-laptop> References: <20180625120304.7543-1-jernej.skrabec@siol.net> <20180625120304.7543-16-jernej.skrabec@siol.net> <1669385.k4L9lni8DF@jernej-laptop> From: Chen-Yu Tsai Date: Thu, 28 Jun 2018 15:00:32 +0800 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [linux-sunxi] Re: [PATCH v3 15/24] dt-bindings: display: sun4i-drm: Add description of A64 HDMI PHY To: Jernej Skrabec Cc: Maxime Ripard , Rob Herring , David Airlie , Gustavo Padovan , Maarten Lankhorst , Sean Paul , Mark Rutland , dri-devel , devicetree , linux-arm-kernel , linux-kernel , linux-clk , linux-sunxi Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8BIT Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Jun 28, 2018 at 12:51 PM, Jernej Škrabec wrote: > Dne četrtek, 28. junij 2018 ob 04:19:55 CEST je Chen-Yu Tsai napisal(a): >> On Mon, Jun 25, 2018 at 8:02 PM, Jernej Skrabec > wrote: >> > A64 HDMI PHY is similar to H3 HDMI PHY except it has two possible PLL >> > clock parents. It is compatible to other HDMI PHYs, like that found in >> > R40. >> > >> > Acked-by: Rob Herring >> > Signed-off-by: Jernej Skrabec >> > --- >> > >> > Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt | 4 +++- >> > 1 file changed, 3 insertions(+), 1 deletion(-) >> > >> > diff --git a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt >> > b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt index >> > 84fe38dbb900..dc83f21ef188 100644 >> > --- a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt >> > +++ b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt >> > @@ -101,6 +101,7 @@ DWC HDMI PHY >> > >> > Required properties: >> > - compatible: value must be one of: >> > + * allwinner,sun50i-a64-hdmi-phy >> > >> > * allwinner,sun8i-a83t-hdmi-phy >> > * allwinner,sun8i-h3-hdmi-phy >> >> Nit: the list is sorted by family first, then SoC name, so it should >> be the last on the list. > > I went alphabetically, since "5" is before "8"... I see. I think version sort applies here, given that sun50i is newer than sun8i. ChenYu > Best regards, > Jernej > >> >> Otherwise, >> >> Reviewed-by: Chen-Yu Tsai >> >> > - reg: base address and size of memory-mapped region >> > >> > @@ -111,8 +112,9 @@ Required properties: >> > - resets: phandle to the reset controller driving the PHY >> > - reset-names: must be "phy" >> > >> > -H3 HDMI PHY requires additional clock: >> > >> > +H3 and A64 HDMI PHY require additional clocks: >> > - pll-0: parent of phy clock >> > >> > + - pll-1: second possible phy clock parent (A64 only) >> > >> > TV Encoder >> > ---------- >> > >> > -- >> > 2.18.0 > > > > > -- > You received this message because you are subscribed to the Google Groups "linux-sunxi" group. > To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscribe@googlegroups.com. > For more options, visit https://groups.google.com/d/optout.