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[209.85.208.179]) by smtp.gmail.com with ESMTPSA id bu9-20020a056512168900b004489c47d241sm1262102lfb.32.2022.03.26.22.21.20 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 26 Mar 2022 22:21:20 -0700 (PDT) Received: by mail-lj1-f179.google.com with SMTP id h11so15167785ljb.2 for ; Sat, 26 Mar 2022 22:21:20 -0700 (PDT) X-Received: by 2002:a2e:6f17:0:b0:248:124:9c08 with SMTP id k23-20020a2e6f17000000b0024801249c08mr14918936ljc.506.1648358479393; Sat, 26 Mar 2022 22:21:19 -0700 (PDT) MIME-Version: 1.0 References: <1812355.tdWV9SEqCh@natalenko.name> <20220324055732.GB12078@lst.de> <4386660.LvFx2qVVIh@natalenko.name> <81ffc753-72aa-6327-b87b-3f11915f2549@arm.com> <878rsza0ih.fsf@toke.dk> <4be26f5d8725cdb016c6fdd9d05cfeb69cdd9e09.camel@freebox.fr> <20220324163132.GB26098@lst.de> <871qyr9t4e.fsf@toke.dk> <20220327054848.1a545b12.pasic@linux.ibm.com> In-Reply-To: From: Linus Torvalds Date: Sat, 26 Mar 2022 22:21:03 -0700 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [REGRESSION] Recent swiotlb DMA_FROM_DEVICE fixes break ath9k-based AP To: Halil Pasic Cc: =?UTF-8?B?VG9rZSBIw7hpbGFuZC1Kw7hyZ2Vuc2Vu?= , Robin Murphy , Christoph Hellwig , Maxime Bizon , Oleksandr Natalenko , Marek Szyprowski , Kalle Valo , "David S. Miller" , Jakub Kicinski , Paolo Abeni , Olha Cherevyk , iommu , linux-wireless , Netdev , Linux Kernel Mailing List , Greg Kroah-Hartman , stable Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Sat, Mar 26, 2022 at 10:06 PM Linus Torvalds wrote: > > On Sat, Mar 26, 2022 at 8:49 PM Halil Pasic wrote: > > > > I agree it CPU modified buffers *concurrently* with DMA can never work, > > and I believe the ownership model was conceived to prevent this > > situation. > > But that just means that the "ownership" model is garbage, and cannot > handle this REAL LIFE situation. Just to clarify: I obviously agree that the "both sides modify concurrently" obviously cannot work with bounce buffers. People still do want to do that, but they'll limit themselves to actual cache-coherent DMA when they do so (or do nasty uncached accesses but at least no bounce buffering). But the "bounce ownership back and forth" model comes up empty when the CPU wants to read while the DMA is still going on. And that not only can work, but *has* worked. You could have a new "get me a non-ownership copy" operation of course, but that hits the problem of "which existing drivers need it?" We have no idea, outside of ath9k. This is why I believe we have to keep the existing semantics in a way that keep ath9k - and any number of unknown other drivers - happy. And then for the cases where you want to introduce the zeroing because you don't know how much data the DMA returned - those are the ones you'll have to mark some way. Linus