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[209.85.208.178]) by smtp.gmail.com with ESMTPSA id m10sm1646497lji.72.2020.07.03.18.54.32 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 03 Jul 2020 18:54:32 -0700 (PDT) Received: by mail-lj1-f178.google.com with SMTP id e4so39001630ljn.4 for ; Fri, 03 Jul 2020 18:54:32 -0700 (PDT) X-Received: by 2002:a2e:760b:: with SMTP id r11mr6758558ljc.285.1593827671608; Fri, 03 Jul 2020 18:54:31 -0700 (PDT) MIME-Version: 1.0 References: <20200701195914.GK2786714@ZenIV.linux.org.uk> <87lfk26nx4.fsf@mpe.ellerman.id.au> <20200702201755.GO2786714@ZenIV.linux.org.uk> <20200702205902.GP2786714@ZenIV.linux.org.uk> <20200703013328.GQ2786714@ZenIV.linux.org.uk> <20200703210237.GS2786714@ZenIV.linux.org.uk> <20200704004959.GY2786714@ZenIV.linux.org.uk> In-Reply-To: <20200704004959.GY2786714@ZenIV.linux.org.uk> From: Linus Torvalds Date: Fri, 3 Jul 2020 18:54:15 -0700 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: objtool clac/stac handling change.. To: Al Viro Cc: Michael Ellerman , Christophe Leroy , Josh Poimboeuf , Peter Zijlstra , "the arch/x86 maintainers" , Linux Kernel Mailing List Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Jul 3, 2020 at 5:50 PM Al Viro wrote: > > How could prefetcht0 possibly > raise an exception? Intel manual says that the only exception is #UD if > LOCK PREFETCHT0 is encountered; not here, obviously. AMD manual simply > says "no exceptions". Confused... Several CPU bugs in this area. I think they may all have been AMD. But we've definitely had "prefetch causes page faults" errata. Google for it. One pdf (AMD errata) I found had this: "Software Prefetches May Report A Page Fault Description Software prefetch instructions are defined to ignore page faults. Under highly specific and detailed internal circumstances, a prefetch instruction may report a page fault if both of the following conditions are true: =E2=80=A2 The target address of the prefetch would cause a page fault if the address was accessed by an actual memory load or store instruction under the current privilege mode; =E2=80=A2 The prefetch instruction is followed in execution-order by an actual or speculative byte-sized memory access of the same modify-intent to the same address. PREFETCH and PREFETCHNTA/0/1/2 have the same modify-intent as a memory load access. PREFETCHW has the same modify-intent as a memory store access. The page fault exception error code bits for the faulting prefetch will be identical to that for a bytesized memory access of the same-modify intent to the same address. Note that some misaligned accesses can be broken up by the processor into multiple accesses where at least one of the accesses is a byte-sized access. If the target address of the subsequent memory access of the same modify-intent is aligned and not byte-sized, this errata does not occur and no workaround is needed. Potential Effect on System An unexpected page fault may occur infrequently on a prefetch instruction." So sadly the architecture manuals do not reflect reality. That said, software prefetch instructions very seldom actually work. They are only useful if you have one _very_ specific load and run one one _very_ specific micrcoarchiecture. Ir's almost always a mistake to have them in the first place. Linus