Re: [PATCH v3 2/2] pinctrl: Add Intel Keem Bay pinctrl driver

[Andy Shevchenko <andy.shevchenko@gmail.com>]

On Fri, Jul 30, 2021 at 12:14 PM Linus Walleij <linus.walleij@linaro.org> wrote:
> On Fri, Jul 16, 2021 at 6:27 PM <lakshmi.sowjanya.d@intel.com> wrote:
>
> > +       /*
> > +        * Each Interrupt line can be shared by up to 4 GPIO pins. Enable bit
> > +        * and input values were checked to identify the source of the
> > +        * Interrupt. The checked enable bit positions are 7, 15, 23 and 31.
> > +        */
> > +       for_each_set_clump8(bit, clump, &reg, BITS_PER_TYPE(typeof(reg))) {
> > +               pin = clump & ~KEEMBAY_GPIO_IRQ_ENABLE;
> > +               val = keembay_read_pin(kpc->base0 + KEEMBAY_GPIO_DATA_IN, pin);
> > +               kmb_irq = irq_linear_revmap(gc->irq.domain, pin);
> > +
> > +               /* Checks if the interrupt is enabled */
> > +               if (val && (clump & KEEMBAY_GPIO_IRQ_ENABLE))
> > +                       generic_handle_irq(kmb_irq);
> > +       }
>
> Aha there it is. "Half-hierarchical" with one IRQ handling 4 lines.
>
> OK we can't do any better than this so this and the bindings
> look fine.
>
> I need to know how Andy think about merging,

Linus, unfortunately I can fulfil a detailed review (busy with a
critical task not related to this platform anyway), but this version
is more or less okay to merge. We may adjust it with follow up fixes
if needed.

>  and then there is
> an uninitialized ret in the mail from Dan Carpenter look into that
> too.
>
> In any case with minor nits fixed:
> Reviewed-by: Linus Walleij <linus.walleij@linaro.org>


-- 
With Best Regards,
Andy Shevchenko