From: Andy Shevchenko <andy.shevchenko@gmail.com>
To: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Cc: Marc Zyngier <maz@kernel.org>,
Geert Uytterhoeven <geert+renesas@glider.be>,
Thomas Gleixner <tglx@linutronix.de>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Linus Walleij <linus.walleij@linaro.org>,
Bartosz Golaszewski <brgl@bgdev.pl>,
Thierry Reding <thierry.reding@gmail.com>,
Jonathan Hunter <jonathanh@nvidia.com>,
Bjorn Andersson <bjorn.andersson@linaro.org>,
Andy Gross <agross@kernel.org>,
Philipp Zabel <p.zabel@pengutronix.de>,
"open list:GPIO SUBSYSTEM" <linux-gpio@vger.kernel.org>,
linux-tegra <linux-tegra@vger.kernel.org>,
linux-arm-msm@vger.kernel.org,
devicetree <devicetree@vger.kernel.org>,
Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
Prabhakar <prabhakar.csengg@gmail.com>,
Linux-Renesas <linux-renesas-soc@vger.kernel.org>,
Phil Edworthy <phil.edworthy@renesas.com>,
Biju Das <biju.das.jz@bp.renesas.com>
Subject: Re: [PATCH v4 0/7] Renesas RZ/G2L IRQC support
Date: Wed, 18 May 2022 23:09:58 +0200 [thread overview]
Message-ID: <CAHp75VeyU4Ox76wz9VfT8qEKHsE1eAo2iw27Lro1tmjJB0npMg@mail.gmail.com> (raw)
In-Reply-To: <20220518192924.20948-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
On Wed, May 18, 2022 at 9:29 PM Lad Prabhakar
<prabhakar.mahadev-lad.rj@bp.renesas.com> wrote:
>
> Hi All,
>
> The RZ/G2L Interrupt Controller is a front-end for the GIC found on
> Renesas RZ/G2L SoC's with below pins:
> - IRQ sense select for 8 external interrupts, mapped to 8 GIC SPI
> interrupts
> - GPIO pins used as external interrupt input pins out of GPIOINT0-122 a
> maximum of only 32 can be mapped to 32 GIC SPI interrupts,
> - NMI edge select.
>
> _____________
> | GIC |
> | ________ |
> ____________ | | | |
> NMI --------------------------------->| | SPI0-479 | | GIC-600| |
> _______ | |------------>| | |
> | | | | PPI16-31 | | | |
> | | IRQ0-IRQ7 | IRQC |------------>| | |
> P0_P48_4 --->| GPIO |---------------->| | | |________| |
> | |GPIOINT0-122 | | | |
> | |---------------->| TINT0-31 | | |
> |______| |__________| |____________|
>
> The proposed patches add hierarchical IRQ domain, one in IRQC driver and
> another in pinctrl driver. Upon interrupt requests map the interrupt to
> GIC. Out of GPIOINT0-122 only 32 can be mapped to GIC SPI, this mapping is
> handled by the pinctrl and IRQC driver.
Where is the explanation on why valid_mask can't be used instead?
--
With Best Regards,
Andy Shevchenko
next prev parent reply other threads:[~2022-05-18 21:10 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-05-18 19:29 [PATCH v4 0/7] Renesas RZ/G2L IRQC support Lad Prabhakar
2022-05-18 19:29 ` [PATCH v4 1/7] dt-bindings: interrupt-controller: Add Renesas RZ/G2L Interrupt Controller Lad Prabhakar
2022-05-18 19:29 ` [PATCH v4 2/7] irqchip: Add RZ/G2L IA55 Interrupt Controller driver Lad Prabhakar
2022-05-18 19:29 ` [PATCH v4 3/7] gpio: gpiolib: Add ngirq member to struct gpio_irq_chip Lad Prabhakar
2022-05-19 13:26 ` Linus Walleij
2022-05-23 17:27 ` Lad, Prabhakar
2022-05-18 19:29 ` [PATCH v4 4/7] gpio: gpiolib: Dont assume child_offset_to_irq callback always succeeds Lad Prabhakar
2022-05-19 13:30 ` Linus Walleij
2022-05-18 19:29 ` [PATCH v4 5/7] gpio: gpiolib: Add a check to validate GPIO hwirq Lad Prabhakar
2022-05-18 21:08 ` Andy Shevchenko
2022-05-19 4:11 ` Lad, Prabhakar
2022-05-18 19:29 ` [PATCH v4 6/7] dt-bindings: pinctrl: renesas,rzg2l-pinctrl: Document the properties to handle GPIO IRQ Lad Prabhakar
2022-05-19 12:01 ` Geert Uytterhoeven
2022-05-23 17:29 ` Lad, Prabhakar
2022-05-18 19:29 ` [PATCH v4 7/7] pinctrl: renesas: pinctrl-rzg2l: Add IRQ domain to handle GPIO interrupt Lad Prabhakar
2022-05-18 21:09 ` Andy Shevchenko [this message]
2022-05-19 4:07 ` [PATCH v4 0/7] Renesas RZ/G2L IRQC support Lad, Prabhakar
2022-05-19 6:58 ` Biju Das
2022-05-23 17:28 ` Lad, Prabhakar
2022-05-19 10:07 ` Andy Shevchenko
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