Re: [PATCH v3 0/6] RTL8231 GPIO expander support

From: Andy Shevchenko <andy.shevchenko@gmail.com>
To: Sander Vanheule <sander@svanheule.net>
Cc: Andrew Lunn <andrew@lunn.ch>, Pavel Machek <pavel@ucw.cz>,
	Rob Herring <robh+dt@kernel.org>,
	Lee Jones <lee.jones@linaro.org>, Mark Brown <broonie@kernel.org>,
	Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
	"Rafael J . Wysocki" <rafael@kernel.org>,
	Michael Walle <michael@walle.cc>,
	Linus Walleij <linus.walleij@linaro.org>,
	Bartosz Golaszewski <bgolaszewski@baylibre.com>,
	Linux LED Subsystem <linux-leds@vger.kernel.org>,
	devicetree <devicetree@vger.kernel.org>,
	"open list:GPIO SUBSYSTEM" <linux-gpio@vger.kernel.org>,
	Linux Kernel Mailing List <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v3 0/6] RTL8231 GPIO expander support
Date: Tue, 25 May 2021 20:11:50 +0300	[thread overview]
Message-ID: <CAHp75VfCBtcQX4rvmQnRMquM0k7ZBqOgZN15Z7TFNSO60SB9TA@mail.gmail.com> (raw)
In-Reply-To: <CAHp75VfzEwVGR7ttdcKzirPDN8oUFw1uTDXPFE=P=9+S3CAFYQ@mail.gmail.com>

On Mon, May 24, 2021 at 7:30 PM Andy Shevchenko
<andy.shevchenko@gmail.com> wrote:
> On Mon, May 24, 2021 at 6:03 PM Sander Vanheule <sander@svanheule.net> wrote:
> > On Mon, 2021-05-24 at 15:54 +0300, Andy Shevchenko wrote:

...

> > Sadly, I don't. Most of the info we have comes from code archives of switch
> > vendors (Zyxel, Cisco etc). Boards need to be reverse engineered, and the few
> > leaked datasheets that can be found on the internet aren't exactly thick in
> > information.
> >
> > The RTL8231 datasheet is actually quite useful, but makes no mention of the
> > output value isse. Since this isn't an official resource, I don't think it would
> > be appropriate to link it via a Datasheet: tag.
> > https://github.com/libc0607/Realtek_switch_hacking/blob/files/RTL8231_Datasheet_
> > 1.2.pdf
> >
> > Looking at the datasheet again, I came up with a... terrible hack to work around
> > the output value issue.
> >
> > The chip also has GPIO_INVERT registers that I hadn't used until now, because
> > the logical inversion is handled in the kernel. However, these inversion
> > registers only apply to the output values. So, I could implement glitch-free
> > output behaviour in the following way:
> >  * After chip reset, and before enabling the output driver (MFD initialisation):
> >     - Mux all pins as GPIO
> >     - Change all pins to outputs,
>
> No. no, no. This is much worse than the glitches. You never know what
> the hardware is connected there and it's potential breakage (on hw
> level) possible.
>
> >  so the data registers (0x1c-0x1e) become writable
> >     - Write value 0 to all pins
> >     - Change all pins to GPI to change them into high-Z
> >  * In the pinctrl/gpio driver:
> >     - Use data registers as input-only
> >     - Use inversion register to determine output value (can be written any time)
> >
> > The above gives glitch-free outputs, but the values that are read back (when
> > configured as output), come from the data registers. They should now be coming
> > from the inversion (reg_set_base) registers, but the code prefers to use the
> > data registers (reg_dat_base).
>
> Lemme read the datasheet and see if I find any clue for the hw behaviour.

Thank you for your patience!

Have you explored the possibility of using En_Sync_GPIO?

-- 
With Best Regards,
Andy Shevchenko