From: Andy Shevchenko <andy.shevchenko@gmail.com>
To: Alban Bedel <alban.bedel@aerq.com>
Cc: "open list:GPIO SUBSYSTEM" <linux-gpio@vger.kernel.org>,
Linus Walleij <linus.walleij@linaro.org>,
Bartosz Golaszewski <bgolaszewski@baylibre.com>,
Linux Kernel Mailing List <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v2] gpio: pca953x: add support for open drain pins on PCAL6524
Date: Mon, 15 Feb 2021 14:53:46 +0200 [thread overview]
Message-ID: <CAHp75VfUY5-VtCWjaU6Q=hJY9hyUz8B36C0528RXUxkbnL9yEA@mail.gmail.com> (raw)
In-Reply-To: <20210211175140.85391-1-alban.bedel@aerq.com>
Hint: don't forget to include reviewers from previous version
On Thu, Feb 11, 2021 at 7:52 PM Alban Bedel <alban.bedel@aerq.com> wrote:
>
> From a quick glance at various datasheets the PCAL6524 and the
> PCAL6534 seems to be the only chips in this family that support
> setting the drive mode of single pins. Other chips either don't
> support it at all, or can only set the drive mode of whole banks,
> which doesn't map to the GPIO API.
>
> Add a new flag, PCAL65xx_REGS, to mark chips that have the extra
> registers needed for this feature. Then mark the needed register banks
> as readable and writable, here we don't set OUT_CONF as writable,
> although it is, as we only need to read it. Finally add a function
> that configures the OUT_INDCONF register when the GPIO API sets the
> drive mode of the pins.
...
> +#define PCAL65xx_REGS BIT(10)
Can we have it as a _TYPE, please?
...
> +#define PCAL65xx_BANK_INDOUT_CONF BIT(8 + 12)
IND is a bit ambiguous based on the description below.
After you elaborate, I probably can propose better naming.
...
> + * - PCAL65xx with individual pin configuration
> + * Individual pin output config 0x40 + 12 * bank_size RW
Not sure I understand what "individual" means here (no, I haven't
looked into the datasheet).
...
> + if (config == PIN_CONFIG_DRIVE_OPEN_DRAIN)
> + val = mask;
> + else if (config == PIN_CONFIG_DRIVE_PUSH_PULL)
> + val = 0;
> + else
> + return -EINVAL;
Switch-case will look more naturally here (despite being longer in
terms of LOCs).
...
> +exit:
exit_unlock:
> + mutex_unlock(&chip->i2c_lock);
> + return ret;
...
> +#define OF_L65XX(__nrgpio) OF_953X(__nrgpio, PCA_LATCH_INT | PCAL65xx_REGS)
When you change to the type, it will go accordingly. Don't add
LATCH_INT to the macro.
--
With Best Regards,
Andy Shevchenko
next prev parent reply other threads:[~2021-02-15 12:55 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-02-11 17:51 [PATCH v2] gpio: pca953x: add support for open drain pins on PCAL6524 Alban Bedel
2021-02-15 12:53 ` Andy Shevchenko [this message]
2021-02-16 16:37 ` Bedel, Alban
2021-02-16 17:50 ` Andy Shevchenko
2021-02-17 13:11 ` Bedel, Alban
2021-02-17 14:19 ` Andy Shevchenko
2021-02-17 18:57 ` Bedel, Alban
2021-02-18 14:14 ` andy.shevchenko
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