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From: Andy Shevchenko <andy.shevchenko@gmail.com>
To: Thomas Gleixner <tglx@linutronix.de>
Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com>,
	Ingo Molnar <mingo@redhat.com>, "H. Peter Anvin" <hpa@zytor.com>,
	"maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT)"
	<x86@kernel.org>, Pavel Tatashin <pasha.tatashin@oracle.com>,
	Linux Kernel Mailing List <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v1 0/6] x86/tsc: Clean up legacy code for Intel MID
Date: Sat, 30 Jun 2018 14:59:08 +0300	[thread overview]
Message-ID: <CAHp75VfY5w_c-V2D6NwraUMxtz_xfAEFanm8jTeF11=nrb5t1Q@mail.gmail.com> (raw)
In-Reply-To: <alpine.DEB.2.21.1806301120010.1595@nanos.tec.linutronix.de>

On Sat, Jun 30, 2018 at 12:24 PM, Thomas Gleixner <tglx@linutronix.de> wrote:
> On Fri, 29 Jun 2018, Andy Shevchenko wrote:
>
>> As Thomas noticed there is unusual initialization is going on on Intel MID
>> platforms when TSC is being calibrated.
>>
>> It appears that we have tsc_msr.c to support Intel MID in a more generic way.
>>
>> So, this patch series removes legacy calibration code and does accompanying
>> clean ups.
>>
>> Has been tested on Intel Medfield and Intel Merrifield platforms.
>
> Nice series from a quick glance! I'll have a deeper look on monday.
>
> One thing on top. From your earlier reply:
>
>> This sounds like a stub against very old calibration code since Intel
>> MID has no PIT, HPET, PMTIMER to calibrate from.
>
> As we already know that the legacy calibration cannot work on those
> machines, we really should splt out the msr/cpuid based calibration method
> into a separate function, which is set for the intel MID stuff and called
> from native_calibrate_tsc/cpu.
>
> Hmm?

But that's what has been done back in 2013! By some reason, I dunno
why, the same author didn't clean up it.


-- 
With Best Regards,
Andy Shevchenko

      reply	other threads:[~2018-06-30 11:59 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-06-29 19:31 [PATCH v1 0/6] x86/tsc: Clean up legacy code for Intel MID Andy Shevchenko
2018-06-29 19:31 ` [PATCH v1 1/6] x86/cpu: Introduce INTEL_CPU_FAM*() helper macros Andy Shevchenko
2018-07-03 11:13   ` [tip:x86/timers] " tip-bot for Andy Shevchenko
2018-06-29 19:31 ` [PATCH v1 2/6] x86/tsc: Convert to use x86_match_cpu() and INTEL_CPU_FAM6() Andy Shevchenko
2018-07-03 11:14   ` [tip:x86/timers] " tip-bot for Andy Shevchenko
2018-06-29 19:31 ` [PATCH v1 3/6] x86/tsc: Add missed header to tsc_msr.c Andy Shevchenko
2018-07-03 11:13   ` [tip:x86/timers] x86/tsc: Add missing " tip-bot for Andy Shevchenko
2018-06-29 19:31 ` [PATCH v1 4/6] x86/tsc: Use SPDX identifier and update Intel copyright Andy Shevchenko
2018-07-03 11:14   ` [tip:x86/timers] " tip-bot for Andy Shevchenko
2018-06-29 19:31 ` [PATCH v1 5/6] x86/platform/intel-mid: Remove custom TSC calibration Andy Shevchenko
2018-07-03 11:15   ` [tip:x86/timers] " tip-bot for Andy Shevchenko
2018-06-29 19:31 ` [PATCH v1 6/6] x86/platform/intel-mid: Remove per platform code Andy Shevchenko
2018-07-03 11:15   ` [tip:x86/timers] " tip-bot for Andy Shevchenko
2018-06-30  9:24 ` [PATCH v1 0/6] x86/tsc: Clean up legacy code for Intel MID Thomas Gleixner
2018-06-30 11:59   ` Andy Shevchenko [this message]

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