From: Mike Leach <mike.leach@linaro.org>
To: Mathieu Poirier <mathieu.poirier@linaro.org>
Cc: linux-arm-kernel <linux-arm-kernel@lists.infradead.org>,
Coresight ML <coresight@lists.linaro.org>,
"open list:DOCUMENTATION" <linux-doc@vger.kernel.org>,
"Suzuki K. Poulose" <suzuki.poulose@arm.com>,
Yabin Cui <yabinc@google.com>, Jonathan Corbet <corbet@lwn.net>,
Leo Yan <leo.yan@linaro.org>,
Alexander Shishkin <alexander.shishkin@linux.intel.com>,
Tingwei Zhang <tingwei@codeaurora.org>,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
Linux Kernel Mailing List <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v4 01/10] coresight: syscfg: Initial coresight system configuration
Date: Fri, 26 Feb 2021 19:10:39 +0000 [thread overview]
Message-ID: <CAJ9a7Vjnt1O6btkBFCTqjHDUOCApcjZcLj1ozNbanDrs6FnOyg@mail.gmail.com> (raw)
In-Reply-To: <20210222185055.GA3239381@xps15>
Hi Mathieu,
On Mon, 22 Feb 2021 at 18:50, Mathieu Poirier
<mathieu.poirier@linaro.org> wrote:
>
> On Thu, Jan 28, 2021 at 05:09:27PM +0000, Mike Leach wrote:
> > Creates an system management API to allow complex configurations and
> > features to be programmed into a CoreSight infrastructure.
> >
> > A feature is defined as a programming set for a device or class of
> > devices.
> >
> > A configuration is a set of features across the system that are enabled
> > for a trace session.
> >
> > The API will manage system wide configuration, and allow complex
> > programmed features to be added to individual device instances, and
> > provide for system wide configuration selection on trace capture
> > operations.
> >
> > This patch creates the initial data object and the initial API for
> > loading configurations and features.
> >
> > Signed-off-by: Mike Leach <mike.leach@linaro.org>
> > ---
> > drivers/hwtracing/coresight/Makefile | 2 +-
> > .../hwtracing/coresight/coresight-config.h | 167 +++++++++++++++
> > drivers/hwtracing/coresight/coresight-core.c | 12 +-
> > .../hwtracing/coresight/coresight-etm-perf.c | 2 +-
> > .../hwtracing/coresight/coresight-etm-perf.h | 2 +-
> > .../hwtracing/coresight/coresight-syscfg.c | 197 ++++++++++++++++++
> > .../hwtracing/coresight/coresight-syscfg.h | 54 +++++
> > 7 files changed, 432 insertions(+), 4 deletions(-)
> > create mode 100644 drivers/hwtracing/coresight/coresight-config.h
> > create mode 100644 drivers/hwtracing/coresight/coresight-syscfg.c
> > create mode 100644 drivers/hwtracing/coresight/coresight-syscfg.h
> >
> > diff --git a/drivers/hwtracing/coresight/Makefile b/drivers/hwtracing/coresight/Makefile
> > index f20e357758d1..4ce854c434b1 100644
> > --- a/drivers/hwtracing/coresight/Makefile
> > +++ b/drivers/hwtracing/coresight/Makefile
> > @@ -4,7 +4,7 @@
> > #
> > obj-$(CONFIG_CORESIGHT) += coresight.o
> > coresight-y := coresight-core.o coresight-etm-perf.o coresight-platform.o \
> > - coresight-sysfs.o
> > + coresight-sysfs.o coresight-syscfg.o
> > obj-$(CONFIG_CORESIGHT_LINK_AND_SINK_TMC) += coresight-tmc.o
> > coresight-tmc-y := coresight-tmc-core.o coresight-tmc-etf.o \
> > coresight-tmc-etr.o
> > diff --git a/drivers/hwtracing/coresight/coresight-config.h b/drivers/hwtracing/coresight/coresight-config.h
> > new file mode 100644
> > index 000000000000..3fedf8ab3cee
> > --- /dev/null
> > +++ b/drivers/hwtracing/coresight/coresight-config.h
> > @@ -0,0 +1,167 @@
> > +/* SPDX-License-Identifier: GPL-2.0 */
> > +/*
> > + * Copyright (c) 2020 Linaro Limited, All rights reserved.
> > + * Author: Mike Leach <mike.leach@linaro.org>
> > + */
> > +
> > +#ifndef _CORESIGHT_CORESIGHT_CONFIG_H
> > +#define _CORESIGHT_CORESIGHT_CONFIG_H
> > +
> > +#include <linux/coresight.h>
> > +#include <linux/types.h>
> > +
> > +/* CoreSight Configuration Management - component and system wide configuration */
> > +
> > +/*
> > + * Register type flags for register value descriptor:
> > + * describe how the value is interpreted, and handled.
> > + */
> > +#define CS_CFG_REG_TYPE_STD 0x80 /* reg is standard reg */
> > +#define CS_CFG_REG_TYPE_RESOURCE 0x40 /* reg is a resource */
> > +#define CS_CFG_REG_TYPE_VAL_PARAM 0x08 /* reg value uses param */
> > +#define CS_CFG_REG_TYPE_VAL_MASK 0x04 /* reg value bit masked */
> > +#define CS_CFG_REG_TYPE_VAL_64BIT 0x02 /* reg value 64 bit */
> > +#define CS_CFG_REG_TYPE_VAL_SAVE 0x01 /* reg value save on disable */
> > +
> > +/*
> > + * flags defining what device class a feature will match to when processing a
> > + * system configuration - used by config data and devices.
> > + */
> > +#define CS_CFG_MATCH_CLASS_SRC_ALL 0x0001 /* match any source */
> > +#define CS_CFG_MATCH_CLASS_SRC_ETM4 0x0002 /* match any ETMv4 device */
> > +
> > +/* flags defining device instance matching - used in config match desc data. */
> > +#define CS_CFG_MATCH_INST_ANY 0x80000000 /* any instance of a class */
> > +
> > +/*
> > + * Limit number of presets in a configuration
> > + * This is related to the number of bits (4) we use to select the preset on
> > + * the perf command line. Preset 0 is always none selected.
> > + * See PMU_FORMAT_ATTR(preset, "config:0-3") in coresight-etm-perf.c
> > + */
> > +#define CS_CFG_CONFIG_PRESET_MAX 15
> > +
> > +/**
> > + * Parameter descriptor for a device feature.
> > + *
> > + * @name: Name of parameter.
> > + * @value: Initial or default value.
> > + */
> > +struct cscfg_parameter_desc {
> > + const char *name;
> > + u64 value;
> > +};
> > +
> > +/**
> > + * Representation of register value.
> > + *
> > + * Supports full 64 bit register value, or 32 bit value with optional mask
> > + * value.
> > + *
> > + * @type: define register usage and interpretation.
> > + * @offset: the address offset for register in the hardware device (per device specification).
> > + * @hw_info: optional hardware device type specific information. (ETM / CTI specific etc)
> > + * @val64: 64 bit value.
> > + * @val32: 32 bit value.
> > + * @mask32: 32 bit mask when using 32 bit value to access device register.
> > + */
> > +struct cscfg_regval_desc {
> > + struct {
> > + u32 type:8;
> > + u32 offset:12;
> > + u32 hw_info:12;
> > + };
> > + union {
> > + u64 val64;
> > + struct {
> > + u32 val32;
> > + u32 mask32;
> > + };
> > + };
> > +};
> > +
> > +/**
> > + * Device feature descriptor - combination of registers and parameters to
> > + * program a device to implement a specific complex function.
> > + *
> > + * @name: feature name.
> > + * @brief: brief description of the feature.
> > + * @item: List entry.
> > + * @match_flags: matching information if loading into a device
> > + * @nr_params: number of parameters used.
> > + * @params: array of parameters used.
> > + * @nr_regs: number of registers used.
> > + * @reg: array of registers used.
> > + */
> > +struct cscfg_feature_desc {
> > + const char *name;
> > + const char *brief;
> > + struct list_head item;
> > + u32 match_flags;
> > + int nr_params;
> > + struct cscfg_parameter_desc *params;
>
> struct cscfg_parameter_desc *params_desc;
>
> > + int nr_regs;
> > + struct cscfg_regval_desc *regs;
>
> struct cscfg_regval_desc *regs_desc;
>
> That way I know exactly what I'm looking at when I see something like the
> following in patch 03:
>
> reg_desc = &feat->desc->regs[i];
>
Agreed - I'll improve the naming consistency in the next revision
Mike
--
Mike Leach
Principal Engineer, ARM Ltd.
Manchester Design Centre. UK
next prev parent reply other threads:[~2021-02-26 19:11 UTC|newest]
Thread overview: 53+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-01-28 17:09 [PATCH v4 00/10] CoreSight configuration management; ETM strobing Mike Leach
2021-01-28 17:09 ` [PATCH v4 01/10] coresight: syscfg: Initial coresight system configuration Mike Leach
2021-02-18 23:52 ` Mathieu Poirier
2021-02-26 19:09 ` Mike Leach
2021-02-22 18:50 ` Mathieu Poirier
2021-02-26 19:10 ` Mike Leach [this message]
2021-03-03 10:09 ` Suzuki K Poulose
2021-03-03 15:12 ` Mike Leach
2021-03-03 10:23 ` Suzuki K Poulose
2021-03-04 10:08 ` Suzuki K Poulose
2021-03-04 10:47 ` Mike Leach
2021-03-04 10:48 ` Suzuki K Poulose
2021-01-28 17:09 ` [PATCH v4 02/10] coresight: syscfg: Add registration and feature loading for cs devices Mike Leach
2021-02-19 18:43 ` Mathieu Poirier
2021-02-26 19:14 ` Mike Leach
2021-02-27 20:52 ` Mathieu Poirier
2021-02-22 17:37 ` Mathieu Poirier
2021-02-26 19:16 ` Mike Leach
2021-02-22 19:05 ` Mathieu Poirier
2021-03-04 10:33 ` Suzuki K Poulose
2021-03-16 18:00 ` Mike Leach
2021-01-28 17:09 ` [PATCH v4 03/10] coresight: config: Add configuration and feature generic functions Mike Leach
2021-02-22 22:57 ` Mathieu Poirier
2021-03-04 11:25 ` Suzuki K Poulose
2021-01-28 17:09 ` [PATCH v4 04/10] coresight: etm-perf: update to handle configuration selection Mike Leach
2021-02-24 18:33 ` Mathieu Poirier
2021-02-26 19:26 ` Mike Leach
2021-03-04 12:13 ` Suzuki K Poulose
2021-03-04 14:19 ` Mike Leach
2021-03-04 14:25 ` Suzuki K Poulose
2021-03-04 14:46 ` Mike Leach
2021-01-28 17:09 ` [PATCH v4 05/10] coresight: syscfg: Add API to activate and enable configurations Mike Leach
2021-02-25 21:20 ` Mathieu Poirier
2021-02-25 21:46 ` Mathieu Poirier
2021-02-26 20:08 ` Mike Leach
2021-03-04 16:49 ` Suzuki K Poulose
2021-03-04 18:15 ` Mike Leach
2021-01-28 17:09 ` [PATCH v4 06/10] coresight: etm-perf: Update to activate selected configuration Mike Leach
2021-02-25 21:51 ` Mathieu Poirier
2021-02-26 20:09 ` Mike Leach
2021-03-04 16:50 ` Suzuki K Poulose
2021-01-28 17:09 ` [PATCH v4 07/10] coresight: etm4x: Add complex configuration handlers to etmv4 Mike Leach
2021-02-28 23:19 ` Mathieu Poirier
2021-03-05 10:18 ` Suzuki K Poulose
2021-03-17 15:04 ` Mike Leach
2021-01-28 17:09 ` [PATCH v4 08/10] coresight: config: Add preloaded configurations Mike Leach
2021-02-28 23:25 ` Mathieu Poirier
2021-03-05 13:39 ` Suzuki K Poulose
2021-01-28 17:09 ` [PATCH v4 09/10] coresight: syscfg: Add initial configfs support Mike Leach
2021-03-01 0:02 ` Mathieu Poirier
2021-03-01 0:04 ` Mathieu Poirier
2021-01-28 17:09 ` [PATCH v4 10/10] coresight: docs: Add documentation for CoreSight config Mike Leach
2021-02-18 21:28 ` Mathieu Poirier
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=CAJ9a7Vjnt1O6btkBFCTqjHDUOCApcjZcLj1ozNbanDrs6FnOyg@mail.gmail.com \
--to=mike.leach@linaro.org \
--cc=alexander.shishkin@linux.intel.com \
--cc=corbet@lwn.net \
--cc=coresight@lists.linaro.org \
--cc=gregkh@linuxfoundation.org \
--cc=leo.yan@linaro.org \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-doc@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=mathieu.poirier@linaro.org \
--cc=suzuki.poulose@arm.com \
--cc=tingwei@codeaurora.org \
--cc=yabinc@google.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).