From: Guo Ren <guoren@kernel.org>
To: "Lad, Prabhakar" <prabhakar.csengg@gmail.com>
Cc: Geert Uytterhoeven <geert+renesas@glider.be>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Magnus Damm <magnus.damm@gmail.com>,
Heiko Stuebner <heiko@sntech.de>,
Conor Dooley <conor.dooley@microchip.com>,
Philipp Tomsich <philipp.tomsich@vrull.eu>,
Nathan Chancellor <nathan@kernel.org>,
Atish Patra <atishp@rivosinc.com>,
Anup Patel <apatel@ventanamicro.com>,
linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org,
Biju Das <biju.das.jz@bp.renesas.com>,
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Subject: Re: [RFC PATCH v2 2/2] soc: renesas: Add L2 cache management for RZ/Five SoC
Date: Wed, 5 Oct 2022 22:23:21 +0800 [thread overview]
Message-ID: <CAJF2gTQ4G-j3p_pHvVQ82R2DFQZq70xgE3ZhoRkxiSzrHnU2og@mail.gmail.com> (raw)
In-Reply-To: <CA+V-a8smkDmQbz76sTA5XfUm7bkY4Ee-L5xYW+-xRWkE1TYiAw@mail.gmail.com>
On Wed, Oct 5, 2022 at 8:54 PM Lad, Prabhakar
<prabhakar.csengg@gmail.com> wrote:
>
> Hi Guo,
>
> On Wed, Oct 5, 2022 at 2:29 AM Guo Ren <guoren@kernel.org> wrote:
> >
> > On Tue, Oct 4, 2022 at 6:32 AM Prabhakar <prabhakar.csengg@gmail.com> wrote:
> > >
> > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > >
> > > On the AX45MP core, cache coherency is a specification option so it may
> > > not be supported. In this case DMA will fail. As a workaround, firstly we
> > > allocate a global dma coherent pool from which DMA allocations are taken
> > > and marked as non-cacheable + bufferable using the PMA region as specified
> > > in the device tree. Synchronization callbacks are implemented to
> > > synchronize when doing DMA transactions.
> > >
> > > The Andes AX45MP core has a Programmable Physical Memory Attributes (PMA)
> > > block that allows dynamic adjustment of memory attributes in the runtime.
> > > It contains a configurable amount of PMA entries implemented as CSR
> > > registers to control the attributes of memory locations in interest.
> > >
> > > Below are the memory attributes supported:
> > > * Device, Non-bufferable
> > > * Device, bufferable
> > > * Memory, Non-cacheable, Non-bufferable
> > > * Memory, Non-cacheable, Bufferable
> > > * Memory, Write-back, No-allocate
> > > * Memory, Write-back, Read-allocate
> > > * Memory, Write-back, Write-allocate
> > > * Memory, Write-back, Read and Write-allocate
> > Seems Svpbmt's PMA, IO, and NC wouldn't fit your requirements, could
> > give a map list of the types of Svpbmt? And give out what you needed,
> > but Svpbmt can't.
> >
> Sorry I didn't get what you meant here, could you please elaborate.
I know there is no pbmt in AX45MP, I am just curious how many physical
memory attributes you would use in linux? It seems only one type used
in the series:
cpu_nocache_area_set -> sbi_ecall(SBI_EXT_ANDES,
SBI_EXT_ANDES_SET_PMA, offset, vaddr, size, entry_id, 0, 0);
I'm not sure how you make emmc/usb/gmac's dma ctrl desc work around
without pbmt when they don't have cache coherency protocol. Do you
need to inject dma_sync for desc synchronization? What's the effect of
dynamic PMA in the patch series?
Thx.
>
> > Here is the Linux dma type to Svpbmt map:
> > PMA -> Normal
> > IO -> ioremap, pgprot_noncached
> > NC -> pgprot_writecombine
> >
> > How about AX45MP?
> >
> Svpbmt extension is not supported on AX45MP (reported by
> riscv_isa_extension_available())
>
> Cheers,
> Prabhakar
--
Best Regards
Guo Ren
next prev parent reply other threads:[~2022-10-05 14:23 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-03 22:32 [RFC PATCH v2 0/2] AX45MP: Add support to non-coherent DMA Prabhakar
2022-10-03 22:32 ` [RFC PATCH v2 1/2] dt-bindings: soc: renesas: r9a07g043f-l2-cache: Add DT binding documentation for L2 cache controller Prabhakar
2022-10-04 6:41 ` Geert Uytterhoeven
2022-10-04 7:26 ` Lad, Prabhakar
2022-10-04 7:31 ` Conor Dooley
2022-10-04 7:59 ` Lad, Prabhakar
2022-10-04 9:12 ` Geert Uytterhoeven
2022-10-04 9:31 ` Lad, Prabhakar
2022-10-04 7:33 ` Conor Dooley
2022-10-03 22:32 ` [RFC PATCH v2 2/2] soc: renesas: Add L2 cache management for RZ/Five SoC Prabhakar
2022-10-04 17:42 ` Conor Dooley
2022-10-05 8:44 ` Lad, Prabhakar
2022-10-05 8:58 ` Conor Dooley
2022-10-05 9:17 ` Conor.Dooley
2022-10-05 10:20 ` Lad, Prabhakar
2022-10-05 10:29 ` Conor Dooley
2022-10-05 9:57 ` Arnd Bergmann
2022-10-05 10:14 ` Lad, Prabhakar
2022-10-05 1:28 ` Guo Ren
2022-10-05 12:53 ` Lad, Prabhakar
2022-10-05 14:23 ` Guo Ren [this message]
2022-10-05 15:02 ` Lad, Prabhakar
2022-10-06 0:59 ` Guo Ren
2022-10-06 15:36 ` Lad, Prabhakar
2022-10-11 9:38 ` Lad, Prabhakar
2022-10-11 13:10 ` Guo Ren
2022-10-17 9:39 ` Lad, Prabhakar
2022-10-17 12:36 ` Guo Ren
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