From: Guo Ren <guoren@kernel.org>
To: Heiko Stuebner <heiko@sntech.de>
Cc: Palmer Dabbelt <palmer@dabbelt.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Albert Ou <aou@eecs.berkeley.edu>,
linux-riscv <linux-riscv@lists.infradead.org>,
Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
Wei Fu <wefu@redhat.com>, liush <liush@allwinnertech.com>,
Atish Patra <atishp@atishpatra.org>,
Anup Patel <anup@brainfault.org>,
Drew Fustini <drew@beagleboard.org>,
Christoph Hellwig <hch@lst.de>, Arnd Bergmann <arnd@arndb.de>,
Chen-Yu Tsai <wens@csie.org>, Maxime Ripard <maxime@cerno.tech>,
Greg Favor <gfavor@ventanamicro.com>,
Andrea Mondelli <andrea.mondelli@huawei.com>,
Jonathan Behrens <behrensj@mit.edu>,
"Xinhaoqu (Freddie)" <xinhaoqu@huawei.com>,
Nick Kossifidis <mick@ics.forth.gr>,
Allen Baum <allen.baum@esperantotech.com>,
Josh Scheid <jscheid@ventanamicro.com>,
Richard Trauben <rtrauben@gmail.com>,
Samuel Holland <samuel@sholland.org>,
Christoph Muellner <cmuellner@linux.com>,
Philipp Tomsich <philipp.tomsich@vrull.eu>
Subject: Re: [PATCH 05/12] riscv: extend concatenated alternatives-lines to the same length
Date: Mon, 16 May 2022 14:55:00 +0800 [thread overview]
Message-ID: <CAJF2gTR7WXDNfvxYaSsTaqjinyRBfQsfz+C7HvtKh4qyviFf6w@mail.gmail.com> (raw)
In-Reply-To: <20220511192921.2223629-6-heiko@sntech.de>
Reviewed-by: Guo Ren <guoren@kernel.org>
On Thu, May 12, 2022 at 3:29 AM Heiko Stuebner <heiko@sntech.de> wrote:
>
> ALT_NEW_CONTENT already uses same-length assembler lines, so
> extend this to the other elements as well.
>
> This makes it more readable when these elements need to be extended
> in the future.
>
> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
> Reviewed-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
> ---
> arch/riscv/include/asm/alternative-macros.h | 20 ++++++++++----------
> 1 file changed, 10 insertions(+), 10 deletions(-)
>
> diff --git a/arch/riscv/include/asm/alternative-macros.h b/arch/riscv/include/asm/alternative-macros.h
> index 9e04cd53afc8..8c2bbc7bbe50 100644
> --- a/arch/riscv/include/asm/alternative-macros.h
> +++ b/arch/riscv/include/asm/alternative-macros.h
> @@ -62,14 +62,14 @@
> #include <asm/asm.h>
> #include <linux/stringify.h>
>
> -#define ALT_ENTRY(oldptr, newptr, vendor_id, errata_id, newlen) \
> - RISCV_PTR " " oldptr "\n" \
> - RISCV_PTR " " newptr "\n" \
> - REG_ASM " " vendor_id "\n" \
> - REG_ASM " " newlen "\n" \
> +#define ALT_ENTRY(oldptr, newptr, vendor_id, errata_id, newlen) \
> + RISCV_PTR " " oldptr "\n" \
> + RISCV_PTR " " newptr "\n" \
> + REG_ASM " " vendor_id "\n" \
> + REG_ASM " " newlen "\n" \
> ".word " errata_id "\n"
>
> -#define ALT_NEW_CONTENT(vendor_id, errata_id, enable, new_c) \
> +#define ALT_NEW_CONTENT(vendor_id, errata_id, enable, new_c) \
> ".if " __stringify(enable) " == 1\n" \
> ".pushsection .alternative, \"a\"\n" \
> ALT_ENTRY("886b", "888f", __stringify(vendor_id), __stringify(errata_id), "889f - 888f") \
> @@ -83,10 +83,10 @@
> ".org . - (889b - 888b) + (887b - 886b)\n" \
> ".endif\n"
>
> -#define __ALTERNATIVE_CFG(old_c, new_c, vendor_id, errata_id, enable) \
> - "886 :\n" \
> - old_c "\n" \
> - "887 :\n" \
> +#define __ALTERNATIVE_CFG(old_c, new_c, vendor_id, errata_id, enable) \
> + "886 :\n" \
> + old_c "\n" \
> + "887 :\n" \
> ALT_NEW_CONTENT(vendor_id, errata_id, enable, new_c)
>
> #define _ALTERNATIVE_CFG(old_c, new_c, vendor_id, errata_id, CONFIG_k) \
> --
> 2.35.1
>
--
Best Regards
Guo Ren
ML: https://lore.kernel.org/linux-csky/
next prev parent reply other threads:[~2022-05-16 6:55 UTC|newest]
Thread overview: 37+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-05-11 19:29 [PATCH v10 00/12] riscv: support for Svpbmt and D1 memory types Heiko Stuebner
2022-05-11 19:29 ` [PATCH 01/12] riscv: integrate alternatives better into the main architecture Heiko Stuebner
2022-05-16 6:01 ` Christoph Hellwig
2022-05-16 6:45 ` Guo Ren
2022-05-11 19:29 ` [PATCH 02/12] riscv: allow different stages with alternatives Heiko Stuebner
2022-05-16 6:01 ` Christoph Hellwig
2022-05-16 6:51 ` Guo Ren
2022-05-11 19:29 ` [PATCH 03/12] riscv: implement module alternatives Heiko Stuebner
2022-05-16 6:02 ` Christoph Hellwig
2022-05-16 6:54 ` Guo Ren
2022-05-11 19:29 ` [PATCH 04/12] riscv: implement ALTERNATIVE_2 macro Heiko Stuebner
2022-05-16 6:03 ` Christoph Hellwig
2022-05-16 6:54 ` Guo Ren
2022-05-11 19:29 ` [PATCH 05/12] riscv: extend concatenated alternatives-lines to the same length Heiko Stuebner
2022-05-16 6:03 ` Christoph Hellwig
2022-05-16 6:55 ` Guo Ren [this message]
2022-05-11 19:29 ` [PATCH 06/12] riscv: prevent compressed instructions in alternatives Heiko Stuebner
2022-05-16 6:04 ` Christoph Hellwig
2022-05-16 6:55 ` Guo Ren
2022-05-11 19:29 ` [PATCH 07/12] riscv: move boot alternatives to after fill_hwcap Heiko Stuebner
2022-05-11 19:29 ` [PATCH 08/12] riscv: Fix accessing pfn bits in PTEs for non-32bit variants Heiko Stuebner
2022-05-16 6:04 ` Christoph Hellwig
2022-05-16 6:55 ` Guo Ren
2022-05-23 14:03 ` Alexandre Ghiti
2022-05-25 15:22 ` Heiko Stübner
2022-05-28 8:15 ` Alexandre Ghiti
2022-05-11 19:29 ` [PATCH 09/12] riscv: add RISC-V Svpbmt extension support Heiko Stuebner
2022-05-16 6:10 ` Christoph Hellwig
2022-05-16 9:09 ` Philipp Tomsich
2022-05-16 10:30 ` Heiko Stübner
2022-05-11 19:29 ` [PATCH 10/12] riscv: remove FIXMAP_PAGE_IO and fall back to its default value Heiko Stuebner
2022-05-11 19:29 ` [PATCH 11/12] riscv: don't use global static vars to store alternative data Heiko Stuebner
2022-05-16 6:15 ` Christoph Hellwig
2022-05-11 19:29 ` [PATCH 12/12] riscv: add memory-type errata for T-Head Heiko Stuebner
2022-05-13 13:37 ` Guo Ren
2022-05-13 3:32 ` [PATCH v10 00/12] riscv: support for Svpbmt and D1 memory types Palmer Dabbelt
2022-05-13 21:41 ` Heiko Stuebner
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