From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.0 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9EF69C433E3 for ; Tue, 30 Mar 2021 06:29:00 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 72ACA619AD for ; Tue, 30 Mar 2021 06:29:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231221AbhC3G2a (ORCPT ); Tue, 30 Mar 2021 02:28:30 -0400 Received: from mail.kernel.org ([198.145.29.99]:45464 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230077AbhC3G2E (ORCPT ); Tue, 30 Mar 2021 02:28:04 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id 9F09B61989; Tue, 30 Mar 2021 06:28:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1617085684; bh=nayM5SKcKbHhEUcOm1Bpv22PdU7DGZfI45+sXYoCtTE=; h=References:In-Reply-To:From:Date:Subject:To:Cc:From; b=IMv2XD/wEsVjpGtT55oa1LNc8j8RhbdTKjnNQ5KxitgKHLKqBILXoWrnh+x6ttIrA q1J2ephhR/I+5tbpOWeMuB3USIbVJVtaYngvXciiXFf9EoW5AJMfUlYa/upofTvij7 92BAKbaWUOLgdgyBp9vx8sTXcXC0m/FMahnH8oTzjzNcv1QNpGPFX9wB24ghUbUrxV uJNCGihskGr9rgMAHL/U1Ix6m5+kb2J5EeEygcWzA+S9GwRcZlNAr1DH4PD2CXYBx1 wW2pFlV8bEtbCUoixFLJ4Wcl7LC7ClMjMpphge7lJj98NFp7lmQEnUO+ukZ6tRkNZJ NT3E+9qpRLMIg== Received: by mail-lf1-f50.google.com with SMTP id b4so22056122lfi.6; Mon, 29 Mar 2021 23:28:03 -0700 (PDT) X-Gm-Message-State: AOAM531jSTbFN7ONC7jpkr5E+86oNRWn37+Pxd4iX6hJO3EgmnZyQ63B ieoSyq5ZQ4r4iq+hIY8YQTf0hu7qTOVrJ8V7CSI= X-Google-Smtp-Source: ABdhPJzWJhIlP8ARSkCvemMJ/FDg5buGQEms6F/qyqWvpnvopcR6D0UAUgTZIBVE9j5JQUWiWacZQWv2FbJpDMaNh5s= X-Received: by 2002:a05:6512:3709:: with SMTP id z9mr18100548lfr.557.1617085681939; Mon, 29 Mar 2021 23:28:01 -0700 (PDT) MIME-Version: 1.0 References: <1616868399-82848-1-git-send-email-guoren@kernel.org> <1616868399-82848-4-git-send-email-guoren@kernel.org> In-Reply-To: From: Guo Ren Date: Tue, 30 Mar 2021 14:27:50 +0800 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v4 3/4] locking/qspinlock: Add ARCH_USE_QUEUED_SPINLOCKS_XCHG32 To: Anup Patel Cc: Peter Zijlstra , linux-riscv , Linux Kernel Mailing List , "linux-csky@vger.kernel.org" , linux-arch , Guo Ren , Will Deacon , Ingo Molnar , Waiman Long , Arnd Bergmann , Anup Patel Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Mar 30, 2021 at 12:54 PM Anup Patel wrote: > > > > > -----Original Message----- > > From: Guo Ren > > Sent: 30 March 2021 08:44 > > To: Peter Zijlstra > > Cc: linux-riscv ; Linux Kernel Mailing List > > ; linux-csky@vger.kernel.org; linux-arch > > ; Guo Ren ; Will > > Deacon ; Ingo Molnar ; Waiman > > Long ; Arnd Bergmann ; Anup > > Patel > > Subject: Re: [PATCH v4 3/4] locking/qspinlock: Add > > ARCH_USE_QUEUED_SPINLOCKS_XCHG32 > > > > On Mon, Mar 29, 2021 at 8:50 PM Peter Zijlstra > > wrote: > > > > > > On Mon, Mar 29, 2021 at 08:01:41PM +0800, Guo Ren wrote: > > > > u32 a = 0x55aa66bb; > > > > u16 *ptr = &a; > > > > > > > > CPU0 CPU1 > > > > ========= ========= > > > > xchg16(ptr, new) while(1) > > > > WRITE_ONCE(*(ptr + 1), x); > > > > > > > > When we use lr.w/sc.w implement xchg16, it'll cause CPU0 deadlock. > > > > > > Then I think your LL/SC is broken. > > > > > > That also means you really don't want to build super complex locking > > > primitives on top, because that live-lock will percolate through. > > Do you mean the below implementation has live-lock risk? > > +static __always_inline u32 xchg_tail(struct qspinlock *lock, u32 tail) > > +{ > > + u32 old, new, val = atomic_read(&lock->val); > > + > > + for (;;) { > > + new = (val & _Q_LOCKED_PENDING_MASK) | tail; > > + old = atomic_cmpxchg(&lock->val, val, new); > > + if (old == val) > > + break; > > + > > + val = old; > > + } > > + return old; > > +} > > > > > > > > > > Step 1 would be to get your architecute fixed such that it can provide > > > fwd progress guarantees for LL/SC. Otherwise there's absolutely no > > > point in building complex systems with it. > > > > Quote Waiman's comment [1] on xchg16 optimization: > > > > "This optimization is needed to make the qspinlock achieve performance > > parity with ticket spinlock at light load." > > > > [1] https://lore.kernel.org/kvm/1429901803-29771-6-git-send-email- > > Waiman.Long@hp.com/ > > > > So for a non-xhg16 machine: > > - ticket-lock for small numbers of CPUs > > - qspinlock for large numbers of CPUs > > > > Okay, I'll put all of them into the next patch > > I would suggest to have separate Kconfig opitons for ticket spinlock > in Linux RISC-V which will be disabled by default. This means Linux > RISC-V will use qspinlock by default and use ticket spinlock only when > ticket spinlock kconfig is enabled. OK > > Regards, > Anup -- Best Regards Guo Ren ML: https://lore.kernel.org/linux-csky/