From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752579AbeDKJwu convert rfc822-to-8bit (ORCPT ); Wed, 11 Apr 2018 05:52:50 -0400 Received: from mail.kernel.org ([198.145.29.99]:33592 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752323AbeDKJws (ORCPT ); Wed, 11 Apr 2018 05:52:48 -0400 DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 37D382183D Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=krzk@kernel.org X-Google-Smtp-Source: AIpwx4/R/NUP5DjbEnnk5NAGAte5sUhn+cOm0xeM0b7p+pNl4xx3VlOCoiK7qHPAaFtfNBoZCMbu16ZfTl02YTmnNpA= MIME-Version: 1.0 In-Reply-To: References: <1523210867-3806-1-git-send-email-pawel.mikolaj.chmiel@gmail.com> From: Krzysztof Kozlowski Date: Wed, 11 Apr 2018 11:52:44 +0200 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH] pinctrl/samsung: Correct EINTG banks order To: Tomasz Figa Cc: =?UTF-8?Q?Pawe=C5=82_Chmiel?= , Sylwester Nawrocki , "linus.walleij@linaro.org" , Kukjin Kim , linux-arm-kernel , "moderated list:SAMSUNG SOC CLOCK DRIVERS" , linux-gpio@vger.kernel.org, linux-kernel , Marek Szyprowski Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8BIT Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, Apr 11, 2018 at 10:36 AM, Tomasz Figa wrote: > 2018-04-10 17:38 GMT+09:00 Tomasz Figa : >> 2018-04-10 16:06 GMT+09:00 Krzysztof Kozlowski : >>> On Sun, Apr 8, 2018 at 8:07 PM, Paweł Chmiel >>> wrote: >>>> All banks with GPIO interrupts should be at beginning >>>> of bank array and without any other types of banks between them. >>>> This order is expected by exynos_eint_gpio_irq, when doing >>>> interrupt group to bank translation. >>>> Otherwise, kernel NULL pointer dereference would happen >>>> when trying to handle interrupt, due to wrong bank being looked up. >>>> Observed on s5pv210, when trying to handle gpj0 interrupt, >>>> where kernel was mapping it to gpi bank. >>> >>> Thanks for the patch. The issue looks real although one thing was >>> missed - there is a gap in SVC group between GPK2 and GPL0 (pointed by >>> Marek Szyprowski): >>> >>> 0x0 - EINT_23 - gpk0 >>> 0x1 - EINT_24 - gpk1 >>> 0x2 - EINT_25 - gpk2 >>> 0x4 - EINT_27 - gpl0 >>> 0x7 - EINT_8 - gpm0 >>> >>> Maybe this should be done differently - to remove such hidden >>> requirement entirely in favor of another parameter of >>> EXYNOS_PIN_BANK_EINTG argument? >> >> Perhaps let's limit this patch to s5pv210 and Exynos5410 alone, where >> a simple swap of bank order in the arrays should be okay. >> >> We might also need to have some fixes on 4x12, because I noticed that >> in exynos4x12_pin_banks0[] there is a hole in eint_offsets between >> gpd1 and gpf0 and exynos4x12_pin_banks1[] starts with gpk0 that has >> eint_offset equal to 0x08 (not 0). > > To close the loop, after talking offline and checking the > documentation, Exynos4x12 is fine, because the group numbers in SVC > register actually match what is defined in bank arrays. Great! Thanks for checking. Best regards, Krzysztof