From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.1 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE, SPF_PASS,T_DKIMWL_WL_HIGH,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5FD92C04AB5 for ; Thu, 6 Jun 2019 08:30:00 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 265A0207E0 for ; Thu, 6 Jun 2019 08:30:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1559809800; bh=ESeaKWLmpng3Q+aBMJkSJpHbp1Q/R2v4Qfz1ZOHm59o=; h=References:In-Reply-To:From:Date:Subject:To:Cc:List-ID:From; b=DRrhFyJRAaTwFsXnqMJx818CzkDGUGb1BlusaEeBe//pp1bYWa/F6tvH9I1pF5kwk YAVy5MP0h+DwQKEZzGMojD5qC7WoSHrT04FwNVT8pNxXmYLIX/MYX9wk2syakBOyT5 qfev706iX2MPCm77RBoViHzdD+YowPFmI6wSEyWM= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727271AbfFFI37 (ORCPT ); Thu, 6 Jun 2019 04:29:59 -0400 Received: from mail.kernel.org ([198.145.29.99]:34502 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725782AbfFFI37 (ORCPT ); Thu, 6 Jun 2019 04:29:59 -0400 Received: from mail-lf1-f44.google.com (mail-lf1-f44.google.com [209.85.167.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 653E420872; Thu, 6 Jun 2019 08:29:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1559809797; bh=ESeaKWLmpng3Q+aBMJkSJpHbp1Q/R2v4Qfz1ZOHm59o=; h=References:In-Reply-To:From:Date:Subject:To:Cc:From; b=x9R2XeSmj0RxSVJrxG06per4Q4E/B42sZuKBfMBYKb0C3wnqBFLjltp02lP7WLnZ7 hjcAUZreGW0UznvPtDNZJTJ1Q+wjp6oCDJsDKJPyZm2ziGcyU9oZHIDPP8ASZIJKy8 4vVJ2mgsERIMnB0c7zxXW/zpUv9aNJNhrDymvsfc= Received: by mail-lf1-f44.google.com with SMTP id 136so897075lfa.8; Thu, 06 Jun 2019 01:29:57 -0700 (PDT) X-Gm-Message-State: APjAAAXDQR5tc61eZvHiNS6psdXb2SR6qnbRnuahVme7Kwh5pFXIuChg CFUY02LE1K2fYWKSrfaRPrfH8WzrV9UhmGzmSjc= X-Google-Smtp-Source: APXvYqymdIkWpecNwmxAyH50GinjhOiyhS6qt2bWxoVqqnSWRehZB24PEim8kWmV0V0gLE4yV7FLcVSzw8vFnVCmzfE= X-Received: by 2002:a19:4f50:: with SMTP id a16mr22487584lfk.24.1559809795620; Thu, 06 Jun 2019 01:29:55 -0700 (PDT) MIME-Version: 1.0 References: <20190605165410.14606-1-l.luba@partner.samsung.com> <20190605165410.14606-8-l.luba@partner.samsung.com> In-Reply-To: <20190605165410.14606-8-l.luba@partner.samsung.com> From: Krzysztof Kozlowski Date: Thu, 6 Jun 2019 10:29:44 +0200 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v8 07/13] dt-bindings: memory-controllers: add Exynos5422 DMC device description To: Lukasz Luba Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, "linux-samsung-soc@vger.kernel.org" , =?UTF-8?B?QmFydMWCb21pZWogxbtvxYJuaWVya2lld2ljeg==?= , kgene@kernel.org, Chanwoo Choi , kyungmin.park@samsung.com, Marek Szyprowski , s.nawrocki@samsung.com, myungjoo.ham@samsung.com, keescook@chromium.org, tony@atomide.com, jroedel@suse.de, treding@nvidia.com, digetx@gmail.com, willy.mh.wolff.ml@gmail.com Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, 5 Jun 2019 at 18:54, Lukasz Luba wrote: > > The patch adds description for DT binding for a new Exynos5422 Dynamic > Memory Controller device. > > Signed-off-by: Lukasz Luba > --- > .../memory-controllers/exynos5422-dmc.txt | 84 +++++++++++++++++++ > 1 file changed, 84 insertions(+) > create mode 100644 Documentation/devicetree/bindings/memory-controllers/exynos5422-dmc.txt > > diff --git a/Documentation/devicetree/bindings/memory-controllers/exynos5422-dmc.txt b/Documentation/devicetree/bindings/memory-controllers/exynos5422-dmc.txt > new file mode 100644 > index 000000000000..989ee0839fdf > --- /dev/null > +++ b/Documentation/devicetree/bindings/memory-controllers/exynos5422-dmc.txt > @@ -0,0 +1,84 @@ > +* Exynos5422 frequency and voltage scaling for Dynamic Memory Controller device > + > +The Samsung Exynos5422 SoC has DMC (Dynamic Memory Controller) to which the DRAM > +memory chips are connected. The driver is to monitor the controller in runtime > +and switch frequency and voltage. To monitor the usage of the controller in > +runtime, the driver uses the PPMU (Platform Performance Monitoring Unit), which > +is able to measure the current load of the memory. > +When 'userspace' governor is used for the driver, an application is able to > +switch the DMC and memory frequency. > + > +Required properties for DMC device for Exynos5422: > +- compatible: Should be "samsung,exynos5422-dmc". > +- clocks : list of clock specifiers, must contain an entry for each > + required entry in clock-names for CLK_FOUT_SPLL, CLK_MOUT_SCLK_SPLL, > + CLK_FF_DOUT_SPLL2, CLK_FOUT_BPLL, CLK_MOUT_BPLL, CLK_SCLK_BPLL, > + CLK_MOUT_MX_MSPLL_CCORE, CLK_MOUT_MX_MSPLL_CCORE_PHY, CLK_MOUT_MCLK_CDREX, > + CLK_DOUT_CLK2X_PHY0, CLK_CLKM_PHY0, CLK_CLKM_PHY1 > +- clock-names : should include "fout_spll", "mout_sclk_spll", "ff_dout_spll2", > + "fout_bpll", "mout_bpll", "sclk_bpll", "mout_mx_mspll_ccore", > + "mout_mx_mspll_ccore_phy", "mout_mclk_cdrex", "dout_clk2x_phy0", "clkm_phy0", > + "clkm_phy1" entries > +- devfreq-events : phandles for PPMU devices connected to this DMC. > +- vdd-supply : phandle for voltage regulator which is connected. > +- reg : registers of two CDREX controllers. > +- operating-points-v2 : phandle for OPPs described in v2 definition. > +- device-handle : phandle of the connected DRAM memory device. For more > + information please refer to documentation file: > + Documentation/devicetree/bindings/ddr/lpddr3.txt > +- devfreq-events : phandles of the PPMU events used by the controller. > +- samsung,syscon-clk : phandle of the clock register set used by the controller, > + these registers are used for enabling a 'pause' feature and are not > + exposed by clock framework but they must be used in a safe way. > + The register offsets are in the driver code and specyfic for this SoC > + type. > + > +Example: > + > + ppmu_dmc0_0: ppmu@10d00000 { > + compatible = "samsung,exynos-ppmu"; > + reg = <0x10d00000 0x2000>; > + clocks = <&clock CLK_PCLK_PPMU_DREX0_0>; > + clock-names = "ppmu"; > + events { > + ppmu_event_dmc0_0: ppmu-event3-dmc0_0 { > + event-name = "ppmu-event3-dmc0_0"; > + }; > + }; > + }; > + > + dmc: memory-controller@10c20000 { > + compatible = "samsung,exynos5422-dmc"; > + reg = <0x10c20000 0x100>, <0x10c30000 0x100>, > + clocks = <&clock CLK_FOUT_SPLL>, I think you should not have tab after '='. Instead align consecutive lines with the first one. > + <&clock CLK_MOUT_SCLK_SPLL>, > + <&clock CLK_FF_DOUT_SPLL2>, > + <&clock CLK_FOUT_BPLL>, > + <&clock CLK_MOUT_BPLL>, > + <&clock CLK_SCLK_BPLL>, > + <&clock CLK_MOUT_MX_MSPLL_CCORE>, > + <&clock CLK_MOUT_MX_MSPLL_CCORE_PHY>, > + <&clock CLK_MOUT_MCLK_CDREX>, > + <&clock CLK_DOUT_CLK2X_PHY0>, > + <&clock CLK_CLKM_PHY0>, > + <&clock CLK_CLKM_PHY1>; > + clock-names = "fout_spll", > + "mout_sclk_spll", > + "ff_dout_spll2", > + "fout_bpll", > + "mout_bpll", > + "sclk_bpll", > + "mout_mx_mspll_ccore", > + "mout_mx_mspll_ccore_phy", > + "mout_mclk_cdrex", > + "dout_clk2x_phy0", > + "clkm_phy0", > + "clkm_phy1"; > + operating-points-v2 = <&dmc_opp_table>; > + devfreq-events = <&ppmu_event3_dmc0_0>, <&ppmu_event3_dmc0_1>, > + <&ppmu_event3_dmc1_0>, <&ppmu_event3_dmc1_1>; > + operating-points-v2 = <&dmc_opp_table>; Duplicated property. Beside that: Acked-by: Krzysztof Kozlowski Best regards, Krzysztof > + device-handle = <&samsung_K3QF2F20DB>; > + vdd-supply = <&buck1_reg>; > + samsung,syscon-clk = <&clock>; > + }; > -- > 2.17.1 >