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Mon, 21 Nov 2022 03:25:58 -0800 (PST) MIME-Version: 1.0 References: <20221120082114.3030-1-jszhang@kernel.org> <20221120082114.3030-6-jszhang@kernel.org> <540beefcad5f9921068d54d056f168a4c45ffeaf.camel@icenowy.me> In-Reply-To: <540beefcad5f9921068d54d056f168a4c45ffeaf.camel@icenowy.me> From: Emil Renner Berthing Date: Mon, 21 Nov 2022 12:25:42 +0100 Message-ID: Subject: Re: [PATCH 5/7] riscv: dts: bouffalolab: add the bl808 SoC base device tree To: Icenowy Zheng Cc: Jisheng Zhang , Greg Kroah-Hartman , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Jiri Slaby , linux-serial@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, 21 Nov 2022 at 04:37, Icenowy Zheng wrote: > > =E5=9C=A8 2022-11-20=E6=98=9F=E6=9C=9F=E6=97=A5=E7=9A=84 15:57 +0100=EF= =BC=8CEmil Renner Berthing=E5=86=99=E9=81=93=EF=BC=9A > > On Sun, 20 Nov 2022 at 09:32, Jisheng Zhang > > wrote: > > > > > > Add a baisc dtsi for the bouffalolab bl808 SoC. > > > > > > Signed-off-by: Jisheng Zhang > > > --- > > > arch/riscv/boot/dts/Makefile | 1 + > > > arch/riscv/boot/dts/bouffalolab/bl808.dtsi | 74 > > > ++++++++++++++++++++++ > > > 2 files changed, 75 insertions(+) > > > create mode 100644 arch/riscv/boot/dts/bouffalolab/bl808.dtsi > > > > > > diff --git a/arch/riscv/boot/dts/Makefile > > > b/arch/riscv/boot/dts/Makefile > > > index ff174996cdfd..b525467152b2 100644 > > > --- a/arch/riscv/boot/dts/Makefile > > > +++ b/arch/riscv/boot/dts/Makefile > > > @@ -1,4 +1,5 @@ > > > # SPDX-License-Identifier: GPL-2.0 > > > +subdir-y +=3D bouffalolab > > > subdir-y +=3D sifive > > > subdir-y +=3D starfive > > > subdir-$(CONFIG_SOC_CANAAN_K210_DTB_BUILTIN) +=3D canaan > > > diff --git a/arch/riscv/boot/dts/bouffalolab/bl808.dtsi > > > b/arch/riscv/boot/dts/bouffalolab/bl808.dtsi > > > new file mode 100644 > > > index 000000000000..c98ebb14ee10 > > > --- /dev/null > > > +++ b/arch/riscv/boot/dts/bouffalolab/bl808.dtsi > > > @@ -0,0 +1,74 @@ > > > +// SPDX-License-Identifier: (GPL-2.0+ or MIT) > > > +/* > > > + * Copyright (C) 2022 Jisheng Zhang > > > + */ > > > + > > > +#include > > > + > > > +/ { > > > + compatible =3D "bouffalolab,bl808"; > > > + #address-cells =3D <1>; > > > + #size-cells =3D <1>; > > > + > > > + cpus { > > > + timebase-frequency =3D <1000000>; > > > + #address-cells =3D <1>; > > > + #size-cells =3D <0>; > > > + > > > + cpu0: cpu@0 { > > > + compatible =3D "thead,c906", "riscv"; > > > + device_type =3D "cpu"; > > > + reg =3D <0>; > > > + d-cache-block-size =3D <64>; > > > + d-cache-sets =3D <256>; > > > + d-cache-size =3D <32768>; > > > + i-cache-block-size =3D <64>; > > > + i-cache-sets =3D <128>; > > > + i-cache-size =3D <32768>; > > > + mmu-type =3D "riscv,sv39"; > > > + riscv,isa =3D "rv64imafdc"; > > > + > > > + cpu0_intc: interrupt-controller { > > > + compatible =3D "riscv,cpu-intc"; > > > + interrupt-controller; > > > + #address-cells =3D <0>; > > > + #interrupt-cells =3D <1>; > > > + }; > > > + }; > > > + }; > > > + > > > + xtal: xtal-clk { > > > + compatible =3D "fixed-clock"; > > > + clock-frequency =3D <40000000>; > > > > This was discussed many times before, but I think the conclusion was > > that the frequency is a property of the crystal on the board, so this > > should be 0 in the SoC dtsi, and then overwritten in the board device > > tree. > > But many chips just specify an accepted frequency in their datasheet, > and using a frequency other than this is undefined behavior. Yes, this was the argument in previous discussions, but the conclusion was still that it should go in the board dts. To be clear I'm just summing up the conclusion from previous discussions about this, and have no strong opinion other than we should do the same everywhere. > > > > > + clock-output-names =3D "xtal"; > > > + #clock-cells =3D <0>; > > > + }; > > > + > > > + soc { > > > + compatible =3D "simple-bus"; > > > + ranges; > > > + interrupt-parent =3D <&plic>; > > > + dma-noncoherent; > > > + #address-cells =3D <1>; > > > + #size-cells =3D <1>; > > > + > > > + uart0: serial@30002000 { > > > + compatible =3D "bouffalolab,uart"; > > > + reg =3D <0x30002000 0x1000>; > > > + interrupts =3D <20 IRQ_TYPE_LEVEL_HIGH>; > > > + clocks =3D <&xtal>; > > > + status =3D "disabled"; > > > + }; > > > + > > > + plic: interrupt-controller@e0000000 { > > > + compatible =3D "thead,c900-plic"; > > > + reg =3D <0xe0000000 0x4000000>; > > > + interrupts-extended =3D <&cpu0_intc > > > 0xffffffff>, > > > + <&cpu0_intc 9>; > > > + interrupt-controller; > > > + #address-cells =3D <0>; > > > + #interrupt-cells =3D <2>; > > > + riscv,ndev =3D <64>; > > > + }; > > > + }; > > > +}; > > > -- > > > 2.37.2 > > > > > > > > > _______________________________________________ > > > linux-riscv mailing list > > > linux-riscv@lists.infradead.org > > > http://lists.infradead.org/mailman/listinfo/linux-riscv > > > > _______________________________________________ > > linux-riscv mailing list > > linux-riscv@lists.infradead.org > > http://lists.infradead.org/mailman/listinfo/linux-riscv >