From: Hsin-Yi Wang <hsinyi@chromium.org>
To: Enric Balletbo i Serra <enric.balletbo@collabora.com>
Cc: lkml <linux-kernel@vger.kernel.org>,
Collabora Kernel ML <kernel@collabora.com>,
Matthias Brugger <matthias.bgg@gmail.com>,
Nicolas Boichat <drinkcat@chromium.org>,
Weiyi Lu <weiyi.lu@mediatek.com>,
"moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE"
<linux-arm-kernel@lists.infradead.org>,
"moderated list:ARM/Mediatek SoC support"
<linux-mediatek@lists.infradead.org>
Subject: Re: [PATCH 3/4] soc: mediatek: pm-domains: Add a power domain names for mt8192
Date: Tue, 2 Mar 2021 11:30:18 +0800 [thread overview]
Message-ID: <CAJMQK-iPs8VXfRhq3Kt_sHfY4iyywh4QfkkNC0ABhHJDfjKKNA@mail.gmail.com> (raw)
In-Reply-To: <20210225175000.824661-3-enric.balletbo@collabora.com>
On Fri, Feb 26, 2021 at 1:50 AM Enric Balletbo i Serra
<enric.balletbo@collabora.com> wrote:
>
> Add the power domains names for the mt8192 SoC.
>
> Fixes: a49d5e7a89d6 ("soc: mediatek: pm-domains: Add support for mt8192")
> Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
Reviewed-by: Hsin-Yi Wang <hsinyi@chromium.org>
> ---
>
> drivers/soc/mediatek/mt8192-pm-domains.h | 21 +++++++++++++++++++++
> 1 file changed, 21 insertions(+)
>
> diff --git a/drivers/soc/mediatek/mt8192-pm-domains.h b/drivers/soc/mediatek/mt8192-pm-domains.h
> index 0fdf6dc6231f..543dda70de01 100644
> --- a/drivers/soc/mediatek/mt8192-pm-domains.h
> +++ b/drivers/soc/mediatek/mt8192-pm-domains.h
> @@ -12,6 +12,7 @@
>
> static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = {
> [MT8192_POWER_DOMAIN_AUDIO] = {
> + .name = "audio",
> .sta_mask = BIT(21),
> .ctl_offs = 0x0354,
> .sram_pdn_bits = GENMASK(8, 8),
> @@ -24,6 +25,7 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = {
> },
> },
> [MT8192_POWER_DOMAIN_CONN] = {
> + .name = "conn",
> .sta_mask = PWR_STATUS_CONN,
> .ctl_offs = 0x0304,
> .sram_pdn_bits = 0,
> @@ -45,12 +47,14 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = {
> .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
> },
> [MT8192_POWER_DOMAIN_MFG0] = {
> + .name = "mfg0",
> .sta_mask = BIT(2),
> .ctl_offs = 0x0308,
> .sram_pdn_bits = GENMASK(8, 8),
> .sram_pdn_ack_bits = GENMASK(12, 12),
> },
> [MT8192_POWER_DOMAIN_MFG1] = {
> + .name = "mfg1",
> .sta_mask = BIT(3),
> .ctl_offs = 0x030c,
> .sram_pdn_bits = GENMASK(8, 8),
> @@ -75,36 +79,42 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = {
> },
> },
> [MT8192_POWER_DOMAIN_MFG2] = {
> + .name = "mfg2",
> .sta_mask = BIT(4),
> .ctl_offs = 0x0310,
> .sram_pdn_bits = GENMASK(8, 8),
> .sram_pdn_ack_bits = GENMASK(12, 12),
> },
> [MT8192_POWER_DOMAIN_MFG3] = {
> + .name = "mfg3",
> .sta_mask = BIT(5),
> .ctl_offs = 0x0314,
> .sram_pdn_bits = GENMASK(8, 8),
> .sram_pdn_ack_bits = GENMASK(12, 12),
> },
> [MT8192_POWER_DOMAIN_MFG4] = {
> + .name = "mfg4",
> .sta_mask = BIT(6),
> .ctl_offs = 0x0318,
> .sram_pdn_bits = GENMASK(8, 8),
> .sram_pdn_ack_bits = GENMASK(12, 12),
> },
> [MT8192_POWER_DOMAIN_MFG5] = {
> + .name = "mfg5",
> .sta_mask = BIT(7),
> .ctl_offs = 0x031c,
> .sram_pdn_bits = GENMASK(8, 8),
> .sram_pdn_ack_bits = GENMASK(12, 12),
> },
> [MT8192_POWER_DOMAIN_MFG6] = {
> + .name = "mfg6",
> .sta_mask = BIT(8),
> .ctl_offs = 0x0320,
> .sram_pdn_bits = GENMASK(8, 8),
> .sram_pdn_ack_bits = GENMASK(12, 12),
> },
> [MT8192_POWER_DOMAIN_DISP] = {
> + .name = "disp",
> .sta_mask = BIT(20),
> .ctl_offs = 0x0350,
> .sram_pdn_bits = GENMASK(8, 8),
> @@ -133,6 +143,7 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = {
> },
> },
> [MT8192_POWER_DOMAIN_IPE] = {
> + .name = "ipe",
> .sta_mask = BIT(14),
> .ctl_offs = 0x0338,
> .sram_pdn_bits = GENMASK(8, 8),
> @@ -149,6 +160,7 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = {
> },
> },
> [MT8192_POWER_DOMAIN_ISP] = {
> + .name = "isp",
> .sta_mask = BIT(12),
> .ctl_offs = 0x0330,
> .sram_pdn_bits = GENMASK(8, 8),
> @@ -165,6 +177,7 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = {
> },
> },
> [MT8192_POWER_DOMAIN_ISP2] = {
> + .name = "isp2",
> .sta_mask = BIT(13),
> .ctl_offs = 0x0334,
> .sram_pdn_bits = GENMASK(8, 8),
> @@ -181,6 +194,7 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = {
> },
> },
> [MT8192_POWER_DOMAIN_MDP] = {
> + .name = "mdp",
> .sta_mask = BIT(19),
> .ctl_offs = 0x034c,
> .sram_pdn_bits = GENMASK(8, 8),
> @@ -197,6 +211,7 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = {
> },
> },
> [MT8192_POWER_DOMAIN_VENC] = {
> + .name = "venc",
> .sta_mask = BIT(17),
> .ctl_offs = 0x0344,
> .sram_pdn_bits = GENMASK(8, 8),
> @@ -213,6 +228,7 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = {
> },
> },
> [MT8192_POWER_DOMAIN_VDEC] = {
> + .name = "vdec",
> .sta_mask = BIT(15),
> .ctl_offs = 0x033c,
> .sram_pdn_bits = GENMASK(8, 8),
> @@ -229,12 +245,14 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = {
> },
> },
> [MT8192_POWER_DOMAIN_VDEC2] = {
> + .name = "vdec2",
> .sta_mask = BIT(16),
> .ctl_offs = 0x0340,
> .sram_pdn_bits = GENMASK(8, 8),
> .sram_pdn_ack_bits = GENMASK(12, 12),
> },
> [MT8192_POWER_DOMAIN_CAM] = {
> + .name = "cam",
> .sta_mask = BIT(23),
> .ctl_offs = 0x035c,
> .sram_pdn_bits = GENMASK(8, 8),
> @@ -263,18 +281,21 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = {
> },
> },
> [MT8192_POWER_DOMAIN_CAM_RAWA] = {
> + .name = "cam_rawa",
> .sta_mask = BIT(24),
> .ctl_offs = 0x0360,
> .sram_pdn_bits = GENMASK(8, 8),
> .sram_pdn_ack_bits = GENMASK(12, 12),
> },
> [MT8192_POWER_DOMAIN_CAM_RAWB] = {
> + .name = "cam_rawb",
> .sta_mask = BIT(25),
> .ctl_offs = 0x0364,
> .sram_pdn_bits = GENMASK(8, 8),
> .sram_pdn_ack_bits = GENMASK(12, 12),
> },
> [MT8192_POWER_DOMAIN_CAM_RAWC] = {
> + .name = "cam_rawc",
> .sta_mask = BIT(26),
> .ctl_offs = 0x0368,
> .sram_pdn_bits = GENMASK(8, 8),
> --
> 2.30.0
>
next prev parent reply other threads:[~2021-03-02 8:12 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-02-25 17:49 [PATCH 1/4] soc: mediatek: pm-domains: Add a meaningful power domain name Enric Balletbo i Serra
2021-02-25 17:49 ` [PATCH 2/4] soc: mediatek: pm-domains: Add a power domain names for mt8183 Enric Balletbo i Serra
2021-03-02 3:29 ` Hsin-Yi Wang
2021-02-25 17:49 ` [PATCH 3/4] soc: mediatek: pm-domains: Add a power domain names for mt8192 Enric Balletbo i Serra
2021-03-02 3:30 ` Hsin-Yi Wang [this message]
2021-02-25 17:50 ` [PATCH 4/4] soc: mediatek: pm-domains: Add a power domain names for mt8167 Enric Balletbo i Serra
2021-03-02 3:30 ` Hsin-Yi Wang
2021-03-02 3:29 ` [PATCH 1/4] soc: mediatek: pm-domains: Add a meaningful power domain name Hsin-Yi Wang
2021-04-01 9:36 ` Matthias Brugger
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