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From: "Rafael J. Wysocki" <rafael@kernel.org>
To: Thomas Gleixner <tglx@linutronix.de>,
	Deepak Sharma <deepak.sharma@amd.com>
Cc: "Rafael J. Wysocki" <rafael@kernel.org>,
	Len Brown <len.brown@intel.com>, Pavel Machek <pavel@ucw.cz>,
	Ingo Molnar <mingo@redhat.com>, Borislav Petkov <bp@alien8.de>,
	"the arch/x86 maintainers" <x86@kernel.org>,
	Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
	Linux PM <linux-pm@vger.kernel.org>
Subject: Re: [RESEND PATCH] x86: ACPI: cstate: Optimize C3 entry on AMD CPUs
Date: Fri, 1 Oct 2021 20:46:17 +0200	[thread overview]
Message-ID: <CAJZ5v0ggnbFvpcmKpemF9Kt9hTGNEDHr+zeXhW+yNqz9KSeZsg@mail.gmail.com> (raw)
In-Reply-To: <87wnn3bcas.ffs@tglx>

On Sun, Sep 26, 2021 at 5:13 PM Thomas Gleixner <tglx@linutronix.de> wrote:
>
> On Fri, Sep 24 2021 at 18:48, Rafael J. Wysocki wrote:
>
> > On Fri, Sep 24, 2021 at 8:12 AM Deepak Sharma <deepak.sharma@amd.com> wrote:
> >>
> >> All Zen or newer CPU which support C3 shares cache. Its not necessary to
> >> flush the caches in software before entering C3. This will cause drop in
> >> performance for the cores which share some caches. ARB_DIS is not used
> >> with current AMD C state implementation. So set related flags correctly.
> >>
> >> Signed-off-by: Deepak Sharma <deepak.sharma@amd.com>
> >
> > I'm planning to take this one unless the x86 maintainers have concerns, thanks.
>
> Acked-by: Thomas Gleixner <tglx@linutronix.de>

Thanks!

Applied as 5.16 material, thanks!

  reply	other threads:[~2021-10-01 18:46 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-09-24  6:12 [RESEND PATCH] x86: ACPI: cstate: Optimize C3 entry on AMD CPUs Deepak Sharma
2021-09-24 16:48 ` Rafael J. Wysocki
2021-09-26 15:12   ` Thomas Gleixner
2021-10-01 18:46     ` Rafael J. Wysocki [this message]
2021-09-29  9:20   ` Peter Zijlstra

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