From: "Rafael J. Wysocki" <rafael@kernel.org>
To: puwen@hygon.cn
Cc: Thomas Gleixner <tglx@linutronix.de>,
Ingo Molnar <mingo@redhat.com>, "H. Peter Anvin" <hpa@zytor.com>,
"the arch/x86 maintainers" <x86@kernel.org>,
thomas.lendacky@amd.com, Borislav Petkov <bp@alien8.de>,
Paolo Bonzini <pbonzini@redhat.com>,
"Rafael J. Wysocki" <rjw@rjwysocki.net>,
Viresh Kumar <viresh.kumar@linaro.org>,
Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
linux-arch <linux-arch@vger.kernel.org>,
Linux PM <linux-pm@vger.kernel.org>
Subject: Re: [PATCH v3 15/17] driver/cpufreq: enable Hygon support to cpufreq driver
Date: Sun, 12 Aug 2018 11:55:34 +0200 [thread overview]
Message-ID: <CAJZ5v0izyq2SoUspLPDRM9U7W+-bZPCcQ4C5Zu1hVFDoUj=w1g@mail.gmail.com> (raw)
In-Reply-To: <36b1edf4bd9e203f8e14fa5b90a5a197fdf13898.1533989493.git.puwen@hygon.cn>
On Sat, Aug 11, 2018 at 3:36 PM Pu Wen <puwen@hygon.cn> wrote:
>
> Enable ACPI cpufreq driver support for Hygon by adding family ID check
> along with AMD.
>
> As Hygon platforms have SMBus device(PCI device ID 0x790b), enable Hygon
> support to function amd_freq_sensitivity_init().
>
> Signed-off-by: Pu Wen <puwen@hygon.cn>
Is there any technical difference between HYGON and AMD?
You seem to be mechanically adding X86_VENDOR_HYGON wherever
X86_VENDOR_AMD is used.
> ---
> drivers/cpufreq/acpi-cpufreq.c | 5 +++++
> drivers/cpufreq/amd_freq_sensitivity.c | 9 +++++++--
> 2 files changed, 12 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/cpufreq/acpi-cpufreq.c b/drivers/cpufreq/acpi-cpufreq.c
> index b61f4ec..d62fd37 100644
> --- a/drivers/cpufreq/acpi-cpufreq.c
> +++ b/drivers/cpufreq/acpi-cpufreq.c
> @@ -61,6 +61,7 @@ enum {
>
> #define INTEL_MSR_RANGE (0xffff)
> #define AMD_MSR_RANGE (0x7)
> +#define HYGON_MSR_RANGE (0x7)
>
> #define MSR_K7_HWCR_CPB_DIS (1ULL << 25)
>
> @@ -95,6 +96,7 @@ static bool boost_state(unsigned int cpu)
> rdmsr_on_cpu(cpu, MSR_IA32_MISC_ENABLE, &lo, &hi);
> msr = lo | ((u64)hi << 32);
> return !(msr & MSR_IA32_MISC_ENABLE_TURBO_DISABLE);
> + case X86_VENDOR_HYGON:
> case X86_VENDOR_AMD:
> rdmsr_on_cpu(cpu, MSR_K7_HWCR, &lo, &hi);
> msr = lo | ((u64)hi << 32);
> @@ -113,6 +115,7 @@ static int boost_set_msr(bool enable)
> msr_addr = MSR_IA32_MISC_ENABLE;
> msr_mask = MSR_IA32_MISC_ENABLE_TURBO_DISABLE;
> break;
> + case X86_VENDOR_HYGON:
> case X86_VENDOR_AMD:
> msr_addr = MSR_K7_HWCR;
> msr_mask = MSR_K7_HWCR_CPB_DIS;
> @@ -225,6 +228,8 @@ static unsigned extract_msr(struct cpufreq_policy *policy, u32 msr)
>
> if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
> msr &= AMD_MSR_RANGE;
> + else if (boot_cpu_data.x86_vendor == X86_VENDOR_HYGON)
> + msr &= HYGON_MSR_RANGE;
> else
> msr &= INTEL_MSR_RANGE;
>
> diff --git a/drivers/cpufreq/amd_freq_sensitivity.c b/drivers/cpufreq/amd_freq_sensitivity.c
> index be926d9..4ac7c3c 100644
> --- a/drivers/cpufreq/amd_freq_sensitivity.c
> +++ b/drivers/cpufreq/amd_freq_sensitivity.c
> @@ -111,11 +111,16 @@ static int __init amd_freq_sensitivity_init(void)
> {
> u64 val;
> struct pci_dev *pcidev;
> + unsigned int pci_vendor;
>
> - if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD)
> + if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
> + pci_vendor = PCI_VENDOR_ID_AMD;
> + else if (boot_cpu_data.x86_vendor == X86_VENDOR_HYGON)
> + pci_vendor = PCI_VENDOR_ID_HYGON;
> + else
> return -ENODEV;
>
> - pcidev = pci_get_device(PCI_VENDOR_ID_AMD,
> + pcidev = pci_get_device(pci_vendor,
> PCI_DEVICE_ID_AMD_KERNCZ_SMBUS, NULL);
>
> if (!pcidev) {
> --
> 2.7.4
>
next prev parent reply other threads:[~2018-08-12 9:55 UTC|newest]
Thread overview: 37+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-08-11 13:25 [PATCH v3 00/17] Add support for Hygon Dhyana Family 18h processor Pu Wen
2018-08-11 13:25 ` [PATCH v3 01/17] x86/cpu: create Dhyana init file and register new cpu_dev to system Pu Wen
2018-08-11 13:26 ` [PATCH v3 02/17] x86/cache: get cache size/leaves and setup cache cpumap for Dhyana Pu Wen
2018-08-11 13:26 ` [PATCH v3 03/17] x86/mtrr: get MTRR number and support TOP_MEM2 Pu Wen
2018-08-11 13:26 ` [PATCH v3 04/17] x86/smpboot: smp init nodelay and no flush caches before sleep Pu Wen
2018-08-11 13:27 ` [PATCH v3 05/17] x86/perfctr: return perf counter and event selection bit offset Pu Wen
2018-08-11 13:27 ` [PATCH v3 06/17] x86/nops: init ideal_nops for Hygon Pu Wen
2018-08-11 13:27 ` [PATCH v3 07/17] x86/pci: add Hygon PCI vendor and northbridge support Pu Wen
2018-08-13 22:14 ` Bjorn Helgaas
2018-08-14 4:56 ` Pu Wen
2018-08-11 13:27 ` [PATCH v3 08/17] x86/apic: add modern APIC support for Hygon Pu Wen
2018-08-11 13:28 ` [PATCH v3 09/17] x86/bugs: add lfence mitigation to spectre v2 and no meltdown " Pu Wen
2018-08-11 13:28 ` [PATCH v3 10/17] x86/events: enable Hygon support to PMU infrastructure Pu Wen
2018-08-11 13:28 ` [PATCH v3 11/17] x86/mce: enable Hygon support to MCE infrastructure Pu Wen
2018-08-11 13:29 ` [PATCH v3 12/17] x86/kvm: enable Hygon support to KVM infrastructure Pu Wen
2018-08-11 13:29 ` [PATCH v3 13/17] x86/xen: enable Hygon support to Xen Pu Wen
2018-08-11 14:34 ` Boris Ostrovsky
2018-08-12 8:55 ` Juergen Gross
2018-08-12 13:26 ` Boris Ostrovsky
2018-08-16 13:29 ` Pu Wen
2018-08-17 4:37 ` Boris Ostrovsky
2018-08-16 13:22 ` Pu Wen
2018-08-11 13:29 ` [PATCH v3 14/17] driver/acpi: enable Hygon support to ACPI driver Pu Wen
2018-08-12 10:12 ` Rafael J. Wysocki
2018-08-11 13:29 ` [PATCH v3 15/17] driver/cpufreq: enable Hygon support to cpufreq driver Pu Wen
2018-08-12 9:55 ` Rafael J. Wysocki [this message]
2018-08-13 16:22 ` Pu Wen
2018-08-14 10:11 ` Rafael J. Wysocki
2018-08-14 10:12 ` Rafael J. Wysocki
2018-08-11 13:30 ` [PATCH v3 16/17] driver/edac: enable Hygon support to AMD64 EDAC driver Pu Wen
2018-08-11 19:56 ` Michael Jin
2018-08-11 20:10 ` Michael Jin
2018-08-13 16:19 ` Pu Wen
2018-08-13 16:17 ` Pu Wen
2018-08-13 16:47 ` Michael Jin
2018-08-13 16:18 ` Pu Wen
2018-08-11 13:30 ` [PATCH v3 17/17] tools/cpupower: enable Hygon support to cpupower tool Pu Wen
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