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[209.85.128.44]) by smtp.gmail.com with ESMTPSA id s9sm648ejf.44.2019.10.29.14.30.28 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 29 Oct 2019 14:30:28 -0700 (PDT) Received: by mail-wm1-f44.google.com with SMTP id 22so3972048wms.3 for ; Tue, 29 Oct 2019 14:30:28 -0700 (PDT) X-Received: by 2002:a05:600c:1150:: with SMTP id z16mr6173967wmz.153.1572384627393; Tue, 29 Oct 2019 14:30:27 -0700 (PDT) MIME-Version: 1.0 References: <20190730191303.206365-1-thgarnie@chromium.org> <20190730191303.206365-11-thgarnie@chromium.org> <20190731125306.GU31381@hirez.programming.kicks-ass.net> <20190812125540.GD23772@zn.tnic> In-Reply-To: <20190812125540.GD23772@zn.tnic> From: Thomas Garnier Date: Tue, 29 Oct 2019 14:30:15 -0700 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v9 10/11] x86/paravirt: Adapt assembly for PIE support To: Borislav Petkov Cc: Peter Zijlstra , Kernel Hardening , Kristen Carlson Accardi , Kees Cook , Juergen Gross , Thomas Hellstrom , "VMware, Inc." , Thomas Gleixner , Ingo Molnar , "H. Peter Anvin" , "the arch/x86 maintainers" , virtualization@lists.linux-foundation.org, LKML Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Aug 12, 2019 at 5:54 AM Borislav Petkov wrote: > > On Wed, Jul 31, 2019 at 02:53:06PM +0200, Peter Zijlstra wrote: > > On Tue, Jul 30, 2019 at 12:12:54PM -0700, Thomas Garnier wrote: > > > if PIE is enabled, switch the paravirt assembly constraints to be > > > compatible. The %c/i constrains generate smaller code so is kept by > > > default. > > > > > > Position Independent Executable (PIE) support will allow to extend the > > > KASLR randomization range below 0xffffffff80000000. > > > > > > Signed-off-by: Thomas Garnier > > > Acked-by: Juergen Gross > > > --- > > > arch/x86/include/asm/paravirt_types.h | 25 +++++++++++++++++++++---- > > > 1 file changed, 21 insertions(+), 4 deletions(-) > > > > > > diff --git a/arch/x86/include/asm/paravirt_types.h b/arch/x86/include/asm/paravirt_types.h > > > index 70b654f3ffe5..fd7dc37d0010 100644 > > > --- a/arch/x86/include/asm/paravirt_types.h > > > +++ b/arch/x86/include/asm/paravirt_types.h > > > @@ -338,9 +338,25 @@ extern struct paravirt_patch_template pv_ops; > > > #define PARAVIRT_PATCH(x) \ > > > (offsetof(struct paravirt_patch_template, x) / sizeof(void *)) > > > > > > +#ifdef CONFIG_X86_PIE > > > +#define paravirt_opptr_call "a" > > > +#define paravirt_opptr_type "p" > > > + > > > +/* > > > + * Alternative patching requires a maximum of 7 bytes but the relative call is > > > + * only 6 bytes. If PIE is enabled, add an additional nop to the call > > > + * instruction to ensure patching is possible. > > > + */ > > > +#define PARAVIRT_CALL_POST "nop;" > > > > I'm confused; where does the 7 come from? The relative call is 6 bytes, > > Well, before it, the relative CALL is a CALL reg/mem64, i.e. the target > is mem64. For example: > > > ffffffff81025c45: ff 14 25 68 37 02 82 callq *0xffffffff82023768 > > That address there is practically pv_ops + offset. > > Now, in the opcode bytes you have 0xff opcode, ModRM byte 0x14 and SIB > byte 0x25, and 4 bytes imm32 offset. And this is 7 bytes. > > What it becomes is: > > ffffffff81025cd0: ff 15 fa d9 ff 00 callq *0xffd9fa(%rip) # ffffffff820236d0 > ffffffff81025cd6: 90 nop > > which is a RIP-relative, i.e., opcode 0xff, ModRM byte 0x15 and imm32. > And this is 6 bytes. > > And since the paravirt patching doesn't do NOP padding like the > alternatives patching does, you need to pad with a byte. > > Thomas, please add the gist of this to the comments because this > incomprehensible machinery better be documented as detailed as possible. Sorry for the late reply, busy couple months. Will add it. > > Thx. > > -- > Regards/Gruss, > Boris. > > Good mailing practices for 400: avoid top-posting and trim the reply.