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From: "Clément Péron" <peron.clem@gmail.com>
To: Dinh Nguyen <dinguyen@kernel.org>
Cc: Russell King <linux@armlinux.org.uk>,
	Florian Fainelli <f.fainelli@gmail.com>,
	linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org
Subject: Re: [PATCH] ARM: debug: enable UART1 for socfpga Cyclone5
Date: Tue, 23 Oct 2018 16:44:32 +0200	[thread overview]
Message-ID: <CAJiuCceZr8NsDgBJgA2y61VHdQ3JYQ6_3r4jKooKLbVfRD8eJQ@mail.gmail.com> (raw)
In-Reply-To: <e761c76d-a806-402a-b25b-04aee9329dbc@kernel.org>

HI Dinh,

On Tue, 23 Oct 2018 at 16:04, Dinh Nguyen <dinguyen@kernel.org> wrote:
>
> Hi Clément,
>
> On 10/09/2018 06:28 AM, Clément Péron wrote:
> > Cyclone5 and Arria10 doesn't have the same memory map for UART1.
> >
> > Split the SOCFPGA_UART1 into 2 options to allow debugging on UART1 for Cylone5.
> >
>
> I'm not sure the need for this patch. Are there any cyclone5 based
> boards that has UART1 as the debug uart? I see that all of them are
> using UART0.

There is no upstream device with this UART used. But the board I have
use it, and there is no limitation to not have it available upstream
no ?

Thanks,
Clement

>
> Dinh
>

  reply	other threads:[~2018-10-23 14:44 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-10-09 11:28 Clément Péron
2018-10-23 14:04 ` Dinh Nguyen
2018-10-23 14:44   ` Clément Péron [this message]
2018-10-23 20:35     ` Dinh Nguyen
2018-10-24  6:51       ` Uwe Kleine-König
2018-10-24 14:11         ` Clément Péron
2018-10-25 14:57           ` Dinh Nguyen

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