From: Chuanhong Guo <gch981213@gmail.com>
To: Tudor Ambarus <Tudor.Ambarus@microchip.com>
Cc: bert@biot.com, Miquel Raynal <miquel.raynal@bootlin.com>,
Richard Weinberger <richard@nod.at>,
Vignesh Raghavendra <vigneshr@ti.com>,
Mark Brown <broonie@kernel.org>,
john.garry@huawei.com, Boris Brezillon <bbrezillon@kernel.org>,
vadivel.muruganx.ramuthevar@linux.intel.com,
open list <linux-kernel@vger.kernel.org>,
linux-mtd@lists.infradead.org
Subject: Re: [PATCH] Add spi-nor driver for Realtek RTL838x/RTL839x switch SoCs
Date: Wed, 16 Dec 2020 19:15:47 +0800 [thread overview]
Message-ID: <CAJsYDVKysjbMYrpv52WcY4Vz=Zdrp69gUwHP=VQcUq_3KpzMhQ@mail.gmail.com> (raw)
In-Reply-To: <410ca5c2-96a0-ffd0-e1c0-316fe37ff4d5@microchip.com>
Hi!
On Wed, Dec 16, 2020 at 4:30 PM <Tudor.Ambarus@microchip.com> wrote:
>
> On 12/15/20 11:46 PM, Bert Vermeulen wrote:
> > This driver supports the spiflash core in all RTL838x/RTL839x SoCs,
> > and likely some older models as well (RTL8196C).
> >
> Can we use SPIMEM and move this under drivers/spi/ instead?
>
> Cheers,
> ta
Just took a brief look at the code, and here's my current understanding
of this controller:
1. CS is controlled separately with SFCSR_CSB* bits
2. To write 1-4 bytes, set SFCSR_LEN* and write to SFDR
2. To read 1-4 bytes, set SFCSR_LEN* and read SFDR
If that's true, this is a generic half-duplex spi controller, and the driver
should register a spi_controller with set_cs and transfer_one
implemented.
--
Regards,
Chuanhong Guo
next prev parent reply other threads:[~2020-12-16 11:17 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-12-15 21:46 [PATCH] Add spi-nor driver for Realtek RTL838x/RTL839x switch SoCs Bert Vermeulen
2020-12-16 8:30 ` Tudor.Ambarus
2020-12-16 11:15 ` Chuanhong Guo [this message]
2020-12-19 22:58 ` Bert Vermeulen
2020-12-20 8:51 ` Chuanhong Guo
2020-12-20 15:36 ` Bert Vermeulen
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