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Thu, 08 Jun 2023 02:45:32 -0700 (PDT) MIME-Version: 1.0 References: <20230525-2bab5376987792eab73507ac@orel> In-Reply-To: <20230525-2bab5376987792eab73507ac@orel> From: Haibo Xu Date: Thu, 8 Jun 2023 17:45:21 +0800 Message-ID: Subject: Re: [PATCH v2 11/11] KVM: riscv: selftests: Add get-reg-list test To: Andrew Jones Cc: Haibo Xu , maz@kernel.org, oliver.upton@linux.dev, seanjc@google.com, Paolo Bonzini , Jonathan Corbet , Anup Patel , Atish Patra , Paul Walmsley , Palmer Dabbelt , Albert Ou , Shuah Khan , James Morse , Suzuki K Poulose , Zenghui Yu , David Matlack , Ben Gardon , Vipin Sharma , Colton Lewis , kvm@vger.kernel.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kselftest@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, May 26, 2023 at 1:18=E2=80=AFAM Andrew Jones wrote: > > > + KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_CORE | KVM_REG_R= ISCV_CORE_REG(mode), > > + KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_CSR | KVM_REG_RI= SCV_CSR_REG(sstatus), > > + KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_CSR | KVM_REG_RI= SCV_CSR_REG(sie), > > + KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_CSR | KVM_REG_RI= SCV_CSR_REG(stvec), > > + KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_CSR | KVM_REG_RI= SCV_CSR_REG(sscratch), > > + KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_CSR | KVM_REG_RI= SCV_CSR_REG(sepc), > > + KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_CSR | KVM_REG_RI= SCV_CSR_REG(scause), > > + KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_CSR | KVM_REG_RI= SCV_CSR_REG(stval), > > + KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_CSR | KVM_REG_RI= SCV_CSR_REG(sip), > > + KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_CSR | KVM_REG_RI= SCV_CSR_REG(satp), > > + KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_CSR | KVM_REG_RI= SCV_CSR_REG(scounteren), > > + KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_TIMER | KVM_REG_= RISCV_TIMER_REG(frequency), > > + KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_TIMER | KVM_REG_= RISCV_TIMER_REG(time), > > + KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_TIMER | KVM_REG_= RISCV_TIMER_REG(compare), > > + KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_TIMER | KVM_REG_= RISCV_TIMER_REG(state), > > + KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_ISA_EXT | KVM_RI= SCV_ISA_EXT_A, > > + KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_ISA_EXT | KVM_RI= SCV_ISA_EXT_C, > > + KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_ISA_EXT | KVM_RI= SCV_ISA_EXT_D, > > + KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_ISA_EXT | KVM_RI= SCV_ISA_EXT_F, > > + KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_ISA_EXT | KVM_RI= SCV_ISA_EXT_H, > > + KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_ISA_EXT | KVM_RI= SCV_ISA_EXT_I, > > + KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_ISA_EXT | KVM_RI= SCV_ISA_EXT_M, > > I think all the above should have the size KVM_REG_SIZE_ULONG. Please als= o > test with a 32-bit host. > Hi Andrew, Just noticed the RISC-V 32-bit kvm selftests was not supported currently. Even though I tried to remove the below check for 32-bit, there were still many warning and error messages during compiling. It seems 32-bit KVM selftests was not supported either for ARM/x86. Do we have a plan to support it on risc-v? Regards, Haibo diff --git a/tools/testing/selftests/kvm/include/kvm_util_base.h b/tools/testing/selftests/kvm/include/kvm_util_base.h index ac4aaa21deee..a32ccc06435b 100644 --- a/tools/testing/selftests/kvm/include/kvm_util_base.h +++ b/tools/testing/selftests/kvm/include/kvm_util_base.h @@ -205,9 +205,9 @@ extern enum vm_guest_mode vm_mode_default; #elif defined(__riscv) -#if __riscv_xlen =3D=3D 32 -#error "RISC-V 32-bit kvm selftests not supported" -#endif +//#if __riscv_xlen =3D=3D 32 +//#error "RISC-V 32-bit kvm selftests not supported" +//#endif > > Thanks, > drew