* [PATCH v3 0/6] mmc: tmio: refactor TMIO core a bit and add UniPhier SD/eMMC controller support
@ 2018-08-23 4:44 Masahiro Yamada
2018-08-23 4:44 ` [PATCH v3 1/6] mmc: tmio: replace tmio_mmc_clk_stop() calls with tmio_mmc_set_clock() Masahiro Yamada
` (6 more replies)
0 siblings, 7 replies; 18+ messages in thread
From: Masahiro Yamada @ 2018-08-23 4:44 UTC (permalink / raw)
To: Wolfram Sang, linux-mmc
Cc: Ulf Hansson, linux-renesas-soc, Masami Hiramatsu, Jassi Brar,
Masahiro Yamada, devicetree, linux-kernel, Rob Herring,
Mark Rutland, linux-arm-kernel
Add UniPhier SD/eMMC controller support.
As a preparation, I changed tmio_mmc_set_clock() to a platform hook.
The clock rate setting is platform-specific, and UniPhier variants
will add another way. I thought it would be better to split this
to a hook to avoid a mess.
V3 is rebase on top of Linus' tree.
I dropped 6/7 because Renesas added more quirks
in the current MW.
Masahiro Yamada (6):
mmc: tmio: replace tmio_mmc_clk_stop() calls with tmio_mmc_set_clock()
mmc: tmio: move tmio_mmc_set_clock() to platform hook
dt-bindings: mmc: add DT binding for UniPhier SD/eMMC controller
mmc: uniphier-sd: add UniPhier SD/eMMC controller driver
mmc: renesas_sdhi: merge clk_{start,stop} functions to set_clock
mmc: tmio: refactor CLK_CTL bit calculation
.../devicetree/bindings/mmc/uniphier-sd.txt | 55 ++
MAINTAINERS | 1 +
drivers/mmc/host/Kconfig | 10 +
drivers/mmc/host/Makefile | 1 +
drivers/mmc/host/renesas_sdhi_core.c | 48 +-
drivers/mmc/host/tmio_mmc.c | 56 ++
drivers/mmc/host/tmio_mmc.h | 4 +-
drivers/mmc/host/tmio_mmc_core.c | 92 +--
drivers/mmc/host/uniphier-sd.c | 693 +++++++++++++++++++++
9 files changed, 871 insertions(+), 89 deletions(-)
create mode 100644 Documentation/devicetree/bindings/mmc/uniphier-sd.txt
create mode 100644 drivers/mmc/host/uniphier-sd.c
--
2.7.4
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH v3 1/6] mmc: tmio: replace tmio_mmc_clk_stop() calls with tmio_mmc_set_clock()
2018-08-23 4:44 [PATCH v3 0/6] mmc: tmio: refactor TMIO core a bit and add UniPhier SD/eMMC controller support Masahiro Yamada
@ 2018-08-23 4:44 ` Masahiro Yamada
2018-08-23 4:44 ` [PATCH v3 2/6] mmc: tmio: move tmio_mmc_set_clock() to platform hook Masahiro Yamada
` (5 subsequent siblings)
6 siblings, 0 replies; 18+ messages in thread
From: Masahiro Yamada @ 2018-08-23 4:44 UTC (permalink / raw)
To: Wolfram Sang, linux-mmc
Cc: Ulf Hansson, linux-renesas-soc, Masami Hiramatsu, Jassi Brar,
Masahiro Yamada, linux-kernel
tmio_mmc_clk_stop(host) is equivalent to tmio_mmc_set_clock(host, 0).
This replacement is needed for the next commit.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
---
Changes in v3: None
Changes in v2: None
drivers/mmc/host/tmio_mmc_core.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/mmc/host/tmio_mmc_core.c b/drivers/mmc/host/tmio_mmc_core.c
index 261b4d6..5717ffa 100644
--- a/drivers/mmc/host/tmio_mmc_core.c
+++ b/drivers/mmc/host/tmio_mmc_core.c
@@ -1043,7 +1043,7 @@ static void tmio_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
switch (ios->power_mode) {
case MMC_POWER_OFF:
tmio_mmc_power_off(host);
- tmio_mmc_clk_stop(host);
+ tmio_mmc_set_clock(host, 0);
break;
case MMC_POWER_UP:
tmio_mmc_power_on(host, ios->vdd);
@@ -1310,7 +1310,7 @@ int tmio_mmc_host_probe(struct tmio_mmc_host *_host)
if (pdata->flags & TMIO_MMC_SDIO_IRQ)
_host->sdio_irq_mask = TMIO_SDIO_MASK_ALL;
- tmio_mmc_clk_stop(_host);
+ tmio_mmc_set_clock(_host, 0);
tmio_mmc_reset(_host);
_host->sdcard_irq_mask = sd_ctrl_read16_and_16_as_32(_host, CTL_IRQ_MASK);
@@ -1394,7 +1394,7 @@ int tmio_mmc_host_runtime_suspend(struct device *dev)
tmio_mmc_disable_mmc_irqs(host, TMIO_MASK_ALL);
if (host->clk_cache)
- tmio_mmc_clk_stop(host);
+ tmio_mmc_set_clock(host, 0);
tmio_mmc_clk_disable(host);
--
2.7.4
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH v3 2/6] mmc: tmio: move tmio_mmc_set_clock() to platform hook
2018-08-23 4:44 [PATCH v3 0/6] mmc: tmio: refactor TMIO core a bit and add UniPhier SD/eMMC controller support Masahiro Yamada
2018-08-23 4:44 ` [PATCH v3 1/6] mmc: tmio: replace tmio_mmc_clk_stop() calls with tmio_mmc_set_clock() Masahiro Yamada
@ 2018-08-23 4:44 ` Masahiro Yamada
2018-08-23 4:44 ` [PATCH v3 3/6] dt-bindings: mmc: add DT binding for UniPhier SD/eMMC controller Masahiro Yamada
` (4 subsequent siblings)
6 siblings, 0 replies; 18+ messages in thread
From: Masahiro Yamada @ 2018-08-23 4:44 UTC (permalink / raw)
To: Wolfram Sang, linux-mmc
Cc: Ulf Hansson, linux-renesas-soc, Masami Hiramatsu, Jassi Brar,
Masahiro Yamada, linux-kernel
tmio_mmc_set_clock() is full of quirks because different SoC vendors
extended this in different ways.
The original IP defines the divisor range 1/2 ... 1/512.
bit 7 is set: 1/512
bit 6 is set: 1/256
...
bit 0 is set: 1/4
all bits clear: 1/2
It is platform-dependent how to achieve the 1/1 clock.
I guess the TMIO-MFD variant uses the clock selector outside of this IP,
as far as I see tmio_core_mmc_clk_div() in drivers/mfd/tmio_core.c
I guess bit[7:0]=0xff is Renesas-specific extension.
Socionext (and Panasonic) uses bit 10 (CLKSEL) for 1/1. Also, newer
versions of UniPhier SoC variants use bit 16 for 1/1024.
host->clk_update() is only used by the Renesas variants, whereas
host->set_clk_div() is only used by the TMIO-MFD variants.
To cope with this mess, promote tmio_mmc_set_clock() to a new
platform hook ->set_clock(), and melt the old two hooks into it.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
---
Changes in v3:
- Rebase
Changes in v2: None
drivers/mmc/host/renesas_sdhi_core.c | 62 +++++++++++++++++++++++-
drivers/mmc/host/tmio_mmc.c | 48 +++++++++++++++++++
drivers/mmc/host/tmio_mmc.h | 4 +-
drivers/mmc/host/tmio_mmc_core.c | 92 +++---------------------------------
4 files changed, 117 insertions(+), 89 deletions(-)
diff --git a/drivers/mmc/host/renesas_sdhi_core.c b/drivers/mmc/host/renesas_sdhi_core.c
index 777e32b..cb6e889 100644
--- a/drivers/mmc/host/renesas_sdhi_core.c
+++ b/drivers/mmc/host/renesas_sdhi_core.c
@@ -155,6 +155,66 @@ static unsigned int renesas_sdhi_clk_update(struct tmio_mmc_host *host,
return ret == 0 ? best_freq : clk_get_rate(priv->clk);
}
+static void renesas_sdhi_clk_start(struct tmio_mmc_host *host)
+{
+ sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
+ sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
+
+ /* HW engineers overrode docs: no sleep needed on R-Car2+ */
+ if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2))
+ usleep_range(10000, 11000);
+}
+
+static void renesas_sdhi_clk_stop(struct tmio_mmc_host *host)
+{
+ sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
+ sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
+
+ /* HW engineers overrode docs: no sleep needed on R-Car2+ */
+ if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2))
+ usleep_range(10000, 11000);
+}
+
+static void renesas_sdhi_set_clock(struct tmio_mmc_host *host,
+ unsigned int new_clock)
+{
+ u32 clk = 0, clock;
+
+ if (new_clock == 0) {
+ renesas_sdhi_clk_stop(host);
+ return;
+ }
+ /*
+ * Both HS400 and HS200/SD104 set 200MHz, but some devices need to
+ * set 400MHz to distinguish the CPG settings in HS400.
+ */
+ if (host->mmc->ios.timing == MMC_TIMING_MMC_HS400 &&
+ host->pdata->flags & TMIO_MMC_HAVE_4TAP_HS400 &&
+ new_clock == 200000000)
+ new_clock = 400000000;
+
+ clock = renesas_sdhi_clk_update(host, new_clock) / 512;
+
+ for (clk = 0x80000080; new_clock >= (clock << 1); clk >>= 1)
+ clock <<= 1;
+
+ /* 1/1 clock is option */
+ if ((host->pdata->flags & TMIO_MMC_CLK_ACTUAL) && ((clk >> 22) & 0x1)) {
+ if (!(host->mmc->ios.timing == MMC_TIMING_MMC_HS400))
+ clk |= 0xff;
+ else
+ clk &= ~0xff;
+ }
+
+ sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
+ sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
+ sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, clk & CLK_CTL_DIV_MASK);
+ if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2))
+ usleep_range(10000, 11000);
+
+ renesas_sdhi_clk_start(host);
+}
+
static void renesas_sdhi_clk_disable(struct tmio_mmc_host *host)
{
struct renesas_sdhi *priv = host_to_priv(host);
@@ -620,8 +680,8 @@ int renesas_sdhi_probe(struct platform_device *pdev,
host->write16_hook = renesas_sdhi_write16_hook;
host->clk_enable = renesas_sdhi_clk_enable;
- host->clk_update = renesas_sdhi_clk_update;
host->clk_disable = renesas_sdhi_clk_disable;
+ host->set_clock = renesas_sdhi_set_clock;
host->multi_io_quirk = renesas_sdhi_multi_io_quirk;
host->dma_ops = dma_ops;
diff --git a/drivers/mmc/host/tmio_mmc.c b/drivers/mmc/host/tmio_mmc.c
index 43a2ea5..b031a77 100644
--- a/drivers/mmc/host/tmio_mmc.c
+++ b/drivers/mmc/host/tmio_mmc.c
@@ -13,6 +13,7 @@
* published by the Free Software Foundation.
*/
+#include <linux/delay.h>
#include <linux/device.h>
#include <linux/mfd/core.h>
#include <linux/mfd/tmio.h>
@@ -23,6 +24,52 @@
#include "tmio_mmc.h"
+static void tmio_mmc_clk_start(struct tmio_mmc_host *host)
+{
+ sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
+ sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
+
+ usleep_range(10000, 11000);
+ sd_ctrl_write16(host, CTL_CLK_AND_WAIT_CTL, 0x0100);
+ usleep_range(10000, 11000);
+}
+
+static void tmio_mmc_clk_stop(struct tmio_mmc_host *host)
+{
+ sd_ctrl_write16(host, CTL_CLK_AND_WAIT_CTL, 0x0000);
+ usleep_range(10000, 11000);
+
+ sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
+ sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
+
+ usleep_range(10000, 11000);
+}
+
+static void tmio_mmc_set_clock(struct tmio_mmc_host *host,
+ unsigned int new_clock)
+{
+ u32 clk = 0, clock;
+
+ if (new_clock == 0) {
+ tmio_mmc_clk_stop(host);
+ return;
+ }
+
+ clock = host->mmc->f_min;
+
+ for (clk = 0x80000080; new_clock >= (clock << 1); clk >>= 1)
+ clock <<= 1;
+
+ host->pdata->set_clk_div(host->pdev, (clk >> 22) & 1);
+
+ sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
+ sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
+ sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, clk & CLK_CTL_DIV_MASK);
+ usleep_range(10000, 11000);
+
+ tmio_mmc_clk_start(host);
+}
+
#ifdef CONFIG_PM_SLEEP
static int tmio_mmc_suspend(struct device *dev)
{
@@ -100,6 +147,7 @@ static int tmio_mmc_probe(struct platform_device *pdev)
/* SD control register space size is 0x200, 0x400 for bus_shift=1 */
host->bus_shift = resource_size(res) >> 10;
+ host->set_clock = tmio_mmc_set_clock;
host->mmc->f_max = pdata->hclk;
host->mmc->f_min = pdata->hclk / 512;
diff --git a/drivers/mmc/host/tmio_mmc.h b/drivers/mmc/host/tmio_mmc.h
index 5d141f7..e6aa13a 100644
--- a/drivers/mmc/host/tmio_mmc.h
+++ b/drivers/mmc/host/tmio_mmc.h
@@ -133,7 +133,6 @@ struct tmio_mmc_host {
/* Callbacks for clock / power control */
void (*set_pwr)(struct platform_device *host, int state);
- void (*set_clk_div)(struct platform_device *host, int state);
/* pio related stuff */
struct scatterlist *sg_ptr;
@@ -170,10 +169,9 @@ struct tmio_mmc_host {
/* Mandatory callback */
int (*clk_enable)(struct tmio_mmc_host *host);
+ void (*set_clock)(struct tmio_mmc_host *host, unsigned int clock);
/* Optional callbacks */
- unsigned int (*clk_update)(struct tmio_mmc_host *host,
- unsigned int new_clock);
void (*clk_disable)(struct tmio_mmc_host *host);
int (*multi_io_quirk)(struct mmc_card *card,
unsigned int direction, int blk_size);
diff --git a/drivers/mmc/host/tmio_mmc_core.c b/drivers/mmc/host/tmio_mmc_core.c
index 5717ffa..0611824 100644
--- a/drivers/mmc/host/tmio_mmc_core.c
+++ b/drivers/mmc/host/tmio_mmc_core.c
@@ -160,83 +160,6 @@ static void tmio_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable)
}
}
-static void tmio_mmc_clk_start(struct tmio_mmc_host *host)
-{
- sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
- sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
-
- /* HW engineers overrode docs: no sleep needed on R-Car2+ */
- if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2))
- usleep_range(10000, 11000);
-
- if (host->pdata->flags & TMIO_MMC_HAVE_HIGH_REG) {
- sd_ctrl_write16(host, CTL_CLK_AND_WAIT_CTL, 0x0100);
- usleep_range(10000, 11000);
- }
-}
-
-static void tmio_mmc_clk_stop(struct tmio_mmc_host *host)
-{
- if (host->pdata->flags & TMIO_MMC_HAVE_HIGH_REG) {
- sd_ctrl_write16(host, CTL_CLK_AND_WAIT_CTL, 0x0000);
- usleep_range(10000, 11000);
- }
-
- sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
- sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
-
- /* HW engineers overrode docs: no sleep needed on R-Car2+ */
- if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2))
- usleep_range(10000, 11000);
-}
-
-static void tmio_mmc_set_clock(struct tmio_mmc_host *host,
- unsigned int new_clock)
-{
- u32 clk = 0, clock;
-
- if (new_clock == 0) {
- tmio_mmc_clk_stop(host);
- return;
- }
- /*
- * Both HS400 and HS200/SD104 set 200MHz, but some devices need to
- * set 400MHz to distinguish the CPG settings in HS400.
- */
- if (host->mmc->ios.timing == MMC_TIMING_MMC_HS400 &&
- host->pdata->flags & TMIO_MMC_HAVE_4TAP_HS400 &&
- new_clock == 200000000)
- new_clock = 400000000;
-
- if (host->clk_update)
- clock = host->clk_update(host, new_clock) / 512;
- else
- clock = host->mmc->f_min;
-
- for (clk = 0x80000080; new_clock >= (clock << 1); clk >>= 1)
- clock <<= 1;
-
- /* 1/1 clock is option */
- if ((host->pdata->flags & TMIO_MMC_CLK_ACTUAL) &&
- ((clk >> 22) & 0x1)) {
- if (!(host->mmc->ios.timing == MMC_TIMING_MMC_HS400))
- clk |= 0xff;
- else
- clk &= ~0xff;
- }
-
- if (host->set_clk_div)
- host->set_clk_div(host->pdev, (clk >> 22) & 1);
-
- sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
- sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
- sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, clk & CLK_CTL_DIV_MASK);
- if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2))
- usleep_range(10000, 11000);
-
- tmio_mmc_clk_start(host);
-}
-
static void tmio_mmc_reset(struct tmio_mmc_host *host)
{
/* FIXME - should we set stop clock reg here */
@@ -1043,15 +966,15 @@ static void tmio_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
switch (ios->power_mode) {
case MMC_POWER_OFF:
tmio_mmc_power_off(host);
- tmio_mmc_set_clock(host, 0);
+ host->set_clock(host, 0);
break;
case MMC_POWER_UP:
tmio_mmc_power_on(host, ios->vdd);
- tmio_mmc_set_clock(host, ios->clock);
+ host->set_clock(host, ios->clock);
tmio_mmc_set_bus_width(host, ios->bus_width);
break;
case MMC_POWER_ON:
- tmio_mmc_set_clock(host, ios->clock);
+ host->set_clock(host, ios->clock);
tmio_mmc_set_bus_width(host, ios->bus_width);
break;
}
@@ -1237,7 +1160,7 @@ int tmio_mmc_host_probe(struct tmio_mmc_host *_host)
int ret;
/*
- * Check the sanity of mmc->f_min to prevent tmio_mmc_set_clock() from
+ * Check the sanity of mmc->f_min to prevent host->set_clock() from
* looping forever...
*/
if (mmc->f_min == 0)
@@ -1247,7 +1170,6 @@ int tmio_mmc_host_probe(struct tmio_mmc_host *_host)
_host->write16_hook = NULL;
_host->set_pwr = pdata->set_pwr;
- _host->set_clk_div = pdata->set_clk_div;
ret = tmio_mmc_init_ocr(_host);
if (ret < 0)
@@ -1310,7 +1232,7 @@ int tmio_mmc_host_probe(struct tmio_mmc_host *_host)
if (pdata->flags & TMIO_MMC_SDIO_IRQ)
_host->sdio_irq_mask = TMIO_SDIO_MASK_ALL;
- tmio_mmc_set_clock(_host, 0);
+ _host->set_clock(_host, 0);
tmio_mmc_reset(_host);
_host->sdcard_irq_mask = sd_ctrl_read16_and_16_as_32(_host, CTL_IRQ_MASK);
@@ -1394,7 +1316,7 @@ int tmio_mmc_host_runtime_suspend(struct device *dev)
tmio_mmc_disable_mmc_irqs(host, TMIO_MASK_ALL);
if (host->clk_cache)
- tmio_mmc_set_clock(host, 0);
+ host->set_clock(host, 0);
tmio_mmc_clk_disable(host);
@@ -1415,7 +1337,7 @@ int tmio_mmc_host_runtime_resume(struct device *dev)
tmio_mmc_clk_enable(host);
if (host->clk_cache)
- tmio_mmc_set_clock(host, host->clk_cache);
+ host->set_clock(host, host->clk_cache);
if (host->native_hotplug)
tmio_mmc_enable_mmc_irqs(host,
--
2.7.4
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH v3 3/6] dt-bindings: mmc: add DT binding for UniPhier SD/eMMC controller
2018-08-23 4:44 [PATCH v3 0/6] mmc: tmio: refactor TMIO core a bit and add UniPhier SD/eMMC controller support Masahiro Yamada
2018-08-23 4:44 ` [PATCH v3 1/6] mmc: tmio: replace tmio_mmc_clk_stop() calls with tmio_mmc_set_clock() Masahiro Yamada
2018-08-23 4:44 ` [PATCH v3 2/6] mmc: tmio: move tmio_mmc_set_clock() to platform hook Masahiro Yamada
@ 2018-08-23 4:44 ` Masahiro Yamada
2018-08-23 4:44 ` [PATCH v3 4/6] mmc: uniphier-sd: add UniPhier SD/eMMC controller driver Masahiro Yamada
` (3 subsequent siblings)
6 siblings, 0 replies; 18+ messages in thread
From: Masahiro Yamada @ 2018-08-23 4:44 UTC (permalink / raw)
To: Wolfram Sang, linux-mmc
Cc: Ulf Hansson, linux-renesas-soc, Masami Hiramatsu, Jassi Brar,
Masahiro Yamada, devicetree, linux-kernel, Rob Herring,
Mark Rutland, linux-arm-kernel
This SD/eMMC controller is used for UniPhier SoC family.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Acked-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
---
Changes in v3: None
Changes in v2:
- Rename compatible "socionext,uniphier-sd-v3.1b"
to "socionext,uniphier-sd-v3.1.1"
.../devicetree/bindings/mmc/uniphier-sd.txt | 55 ++++++++++++++++++++++
1 file changed, 55 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mmc/uniphier-sd.txt
diff --git a/Documentation/devicetree/bindings/mmc/uniphier-sd.txt b/Documentation/devicetree/bindings/mmc/uniphier-sd.txt
new file mode 100644
index 0000000..e1d6587
--- /dev/null
+++ b/Documentation/devicetree/bindings/mmc/uniphier-sd.txt
@@ -0,0 +1,55 @@
+UniPhier SD/eMMC controller
+
+Required properties:
+- compatible: should be one of the following:
+ "socionext,uniphier-sd-v2.91" - IP version 2.91
+ "socionext,uniphier-sd-v3.1" - IP version 3.1
+ "socionext,uniphier-sd-v3.1.1" - IP version 3.1.1
+- reg: offset and length of the register set for the device.
+- interrupts: a single interrupt specifier.
+- clocks: a single clock specifier of the controller clock.
+- reset-names: should contain the following:
+ "host" - mandatory for all versions
+ "bridge" - should exist only for "socionext,uniphier-sd-v2.91"
+ "hw" - should exist if eMMC hw reset line is available
+- resets: a list of reset specifiers, corresponding to the reset-names
+
+Optional properties:
+- pinctrl-names: if present, should contain the following:
+ "default" - should exist for all instances
+ "uhs" - should exist for SD instance with UHS support
+- pinctrl-0: pin control state for the default mode
+- pinctrl-1: pin control state for the UHS mode
+- dma-names: should be "rx-tx" if present.
+ This property can exist only for "socionext,uniphier-sd-v2.91".
+- dmas: a single DMA channel specifier
+ This property can exist only for "socionext,uniphier-sd-v2.91".
+- bus-width: see mmc.txt
+- cap-sd-highspeed: see mmc.txt
+- cap-mmc-highspeed: see mmc.txt
+- sd-uhs-sdr12: see mmc.txt
+- sd-uhs-sdr25: see mmc.txt
+- sd-uhs-sdr50: see mmc.txt
+- cap-mmc-hw-reset: should exist if reset-names contains "hw". see mmc.txt
+- non-removable: see mmc.txt
+
+Example:
+
+ sd: sdhc@5a400000 {
+ compatible = "socionext,uniphier-sd-v2.91";
+ reg = <0x5a400000 0x200>;
+ interrupts = <0 76 4>;
+ pinctrl-names = "default", "uhs";
+ pinctrl-0 = <&pinctrl_sd>;
+ pinctrl-1 = <&pinctrl_sd_uhs>;
+ clocks = <&mio_clk 0>;
+ reset-names = "host", "bridge";
+ resets = <&mio_rst 0>, <&mio_rst 3>;
+ dma-names = "rx-tx";
+ dmas = <&dmac 4>;
+ bus-width = <4>;
+ cap-sd-highspeed;
+ sd-uhs-sdr12;
+ sd-uhs-sdr25;
+ sd-uhs-sdr50;
+ };
--
2.7.4
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH v3 4/6] mmc: uniphier-sd: add UniPhier SD/eMMC controller driver
2018-08-23 4:44 [PATCH v3 0/6] mmc: tmio: refactor TMIO core a bit and add UniPhier SD/eMMC controller support Masahiro Yamada
` (2 preceding siblings ...)
2018-08-23 4:44 ` [PATCH v3 3/6] dt-bindings: mmc: add DT binding for UniPhier SD/eMMC controller Masahiro Yamada
@ 2018-08-23 4:44 ` Masahiro Yamada
2018-08-23 10:43 ` Ulf Hansson
2018-08-23 4:44 ` [PATCH v3 5/6] mmc: renesas_sdhi: merge clk_{start,stop} functions to set_clock Masahiro Yamada
` (2 subsequent siblings)
6 siblings, 1 reply; 18+ messages in thread
From: Masahiro Yamada @ 2018-08-23 4:44 UTC (permalink / raw)
To: Wolfram Sang, linux-mmc
Cc: Ulf Hansson, linux-renesas-soc, Masami Hiramatsu, Jassi Brar,
Masahiro Yamada, linux-arm-kernel, linux-kernel
Here is another TMIO MMC variant found in Socionext UniPhier SoCs.
As commit b6147490e6aa ("mmc: tmio: split core functionality, DMA and
MFD glue") said, these MMC controllers use the IP from Panasonic.
However, the MMC controller in the TMIO (Toshiba Mobile IO) MFD chip
was the first upstreamed user of this IP. The common driver code
for this IP is now called 'tmio-mmc-core' in Linux although it is a
historical misnomer.
Anyway, this driver select's MMC_TMIO_CORE to borrow the common code
from tmio-mmc-core.c
Older UniPhier SoCs (LD4, Pro4, sLD8) support the external DMA engine
like renesas_sdhi_sys_dmac.c. The difference is UniPhier SoCs use a
single DMA channel whereas Renesas chips request separate channels for
RX and TX.
Newer UniPhier SoCs (Pro5 and later) support the internal DMA engine
like renesas_sdhi_internal_dmac.c The register map is almost the same,
so I guess Renesas and Socionext use the same internal DMA hardware.
The main difference is, the register offsets are doubled for Renesas.
Renesas Socionext
SDHI UniPhier
DM_CM_DTRAN_MODE 0x820 0x410
DM_CM_DTRAN_CTRL 0x828 0x414
DM_CM_RST 0x830 0x418
DM_CM_INFO1 0x840 0x420
DM_CM_INFO1_MASK 0x848 0x424
DM_CM_INFO2 0x850 0x428
DM_CM_INFO2_MASK 0x858 0x42c
DM_DTRAN_ADDR 0x880 0x440
DM_DTRAN_ADDREX --- 0x444
This comes from the difference of host->bus_shift; 2 for Renesas SoCs,
and 1 for UniPhier SoCs. Also, the datasheet for UniPhier SoCs defines
DM_DTRAN_ADDR and DM_DTRAN_ADDREX as two separate registers.
It could be possible to factor out the DMA common code by introducing
some hooks to cope with platform quirks, but this patch does not touch
that for now.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
---
Changes in v3:
- Fix double dma_unmap_sg for external dma engine
- Add error status handling for DMA callback-result
Changes in v2:
- Rename compatible "socionext,uniphier-sd-v3.1b"
to "socionext,uniphier-sd-v3.1.1"
- Use ->callback_result hook instead of deprecated ->callback
MAINTAINERS | 1 +
drivers/mmc/host/Kconfig | 10 +
drivers/mmc/host/Makefile | 1 +
drivers/mmc/host/uniphier-sd.c | 693 +++++++++++++++++++++++++++++++++++++++++
4 files changed, 705 insertions(+)
create mode 100644 drivers/mmc/host/uniphier-sd.c
diff --git a/MAINTAINERS b/MAINTAINERS
index efb08d7..fb36f44 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2181,6 +2181,7 @@ F: drivers/clk/uniphier/
F: drivers/gpio/gpio-uniphier.c
F: drivers/i2c/busses/i2c-uniphier*
F: drivers/irqchip/irq-uniphier-aidet.c
+F: drivers/mmc/host/uniphier-sd.c
F: drivers/pinctrl/uniphier/
F: drivers/reset/reset-uniphier.c
F: drivers/tty/serial/8250/8250_uniphier.c
diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
index 4dfa67a..d2fe4ce 100644
--- a/drivers/mmc/host/Kconfig
+++ b/drivers/mmc/host/Kconfig
@@ -630,6 +630,16 @@ config MMC_SDHI_INTERNAL_DMAC
using on-chip bus mastering. This supports the controllers
found in arm64 based SoCs.
+config MMC_UNIPHIER
+ tristate "UniPhier SD/eMMC Host Controller support"
+ depends on ARCH_UNIPHIER || COMPILE_TEST
+ depends on OF
+ select MMC_TMIO_CORE
+ help
+ This provides support for the SD/eMMC controller found in
+ UniPhier SoCs. The eMMC variant of this controller is used
+ only for 32-bit SoCs.
+
config MMC_CB710
tristate "ENE CB710 MMC/SD Interface support"
depends on PCI
diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile
index ce8398e..a835d1a 100644
--- a/drivers/mmc/host/Makefile
+++ b/drivers/mmc/host/Makefile
@@ -42,6 +42,7 @@ obj-$(CONFIG_MMC_TMIO_CORE) += tmio_mmc_core.o
obj-$(CONFIG_MMC_SDHI) += renesas_sdhi_core.o
obj-$(CONFIG_MMC_SDHI_SYS_DMAC) += renesas_sdhi_sys_dmac.o
obj-$(CONFIG_MMC_SDHI_INTERNAL_DMAC) += renesas_sdhi_internal_dmac.o
+obj-$(CONFIG_MMC_UNIPHIER) += uniphier-sd.o
obj-$(CONFIG_MMC_CB710) += cb710-mmc.o
obj-$(CONFIG_MMC_VIA_SDMMC) += via-sdmmc.o
octeon-mmc-objs := cavium.o cavium-octeon.o
diff --git a/drivers/mmc/host/uniphier-sd.c b/drivers/mmc/host/uniphier-sd.c
new file mode 100644
index 0000000..10e7b30
--- /dev/null
+++ b/drivers/mmc/host/uniphier-sd.c
@@ -0,0 +1,693 @@
+// SPDX-License-Identifier: GPL-2.0
+//
+// Copyright (C) 2017-2018 Socionext Inc.
+// Author: Masahiro Yamada <yamada.masahiro@socionext.com>
+
+#include <linux/bitfield.h>
+#include <linux/bitops.h>
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/dma-mapping.h>
+#include <linux/mfd/tmio.h>
+#include <linux/mmc/host.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/pinctrl/consumer.h>
+#include <linux/platform_device.h>
+#include <linux/reset.h>
+
+#include "tmio_mmc.h"
+
+#define UNIPHIER_SD_CLK_CTL_DIV1024 BIT(16)
+#define UNIPHIER_SD_CLK_CTL_DIV1 BIT(10)
+#define UNIPHIER_SD_CLKCTL_OFFEN BIT(9) // auto SDCLK stop
+#define UNIPHIER_SD_CC_EXT_MODE 0x1b0
+#define UNIPHIER_SD_CC_EXT_MODE_DMA BIT(1)
+#define UNIPHIER_SD_HOST_MODE 0x1c8
+#define UNIPHIER_SD_VOLT 0x1e4
+#define UNIPHIER_SD_VOLT_MASK GENMASK(1, 0)
+#define UNIPHIER_SD_VOLT_OFF 0
+#define UNIPHIER_SD_VOLT_330 1 // 3.3V signal
+#define UNIPHIER_SD_VOLT_180 2 // 1.8V signal
+#define UNIPHIER_SD_DMA_MODE 0x410
+#define UNIPHIER_SD_DMA_MODE_DIR_MASK GENMASK(17, 16)
+#define UNIPHIER_SD_DMA_MODE_DIR_TO_DEV 0
+#define UNIPHIER_SD_DMA_MODE_DIR_FROM_DEV 1
+#define UNIPHIER_SD_DMA_MODE_WIDTH_MASK GENMASK(5, 4)
+#define UNIPHIER_SD_DMA_MODE_WIDTH_8 0
+#define UNIPHIER_SD_DMA_MODE_WIDTH_16 1
+#define UNIPHIER_SD_DMA_MODE_WIDTH_32 2
+#define UNIPHIER_SD_DMA_MODE_WIDTH_64 3
+#define UNIPHIER_SD_DMA_MODE_ADDR_INC BIT(0) // 1: inc, 0: fixed
+#define UNIPHIER_SD_DMA_CTL 0x414
+#define UNIPHIER_SD_DMA_CTL_START BIT(0) // start DMA (auto cleared)
+#define UNIPHIER_SD_DMA_RST 0x418
+#define UNIPHIER_SD_DMA_RST_CH1 BIT(9)
+#define UNIPHIER_SD_DMA_RST_CH0 BIT(8)
+#define UNIPHIER_SD_DMA_ADDR_L 0x440
+#define UNIPHIER_SD_DMA_ADDR_H 0x444
+
+/*
+ * IP is extended to support various features: built-in DMA engine,
+ * 1/1024 divisor, etc.
+ */
+#define UNIPHIER_SD_CAP_EXTENDED_IP BIT(0)
+/* RX channel of the built-in DMA controller is broken (Pro5) */
+#define UNIPHIER_SD_CAP_BROKEN_DMA_RX BIT(1)
+
+struct uniphier_sd_priv {
+ struct tmio_mmc_data tmio_data;
+ struct pinctrl *pinctrl;
+ struct pinctrl_state *pinstate_default;
+ struct pinctrl_state *pinstate_uhs;
+ struct clk *clk;
+ struct reset_control *rst;
+ struct reset_control *rst_br;
+ struct reset_control *rst_hw;
+ struct dma_chan *chan;
+ enum dma_data_direction dma_dir;
+ unsigned long clk_rate;
+ unsigned long caps;
+};
+
+static void *uniphier_sd_priv(struct tmio_mmc_host *host)
+{
+ return container_of(host->pdata, struct uniphier_sd_priv, tmio_data);
+}
+
+static void uniphier_sd_dma_endisable(struct tmio_mmc_host *host, int enable)
+{
+ sd_ctrl_write16(host, CTL_DMA_ENABLE, DMA_ENABLE_DMASDRW);
+}
+
+/* external DMA engine */
+static void uniphier_sd_external_dma_issue(unsigned long arg)
+{
+ struct tmio_mmc_host *host = (void *)arg;
+ struct uniphier_sd_priv *priv = uniphier_sd_priv(host);
+
+ uniphier_sd_dma_endisable(host, 1);
+ dma_async_issue_pending(priv->chan);
+}
+
+static void uniphier_sd_external_dma_callback(void *param,
+ const struct dmaengine_result *result)
+{
+ struct tmio_mmc_host *host = param;
+ struct uniphier_sd_priv *priv = uniphier_sd_priv(host);
+ unsigned long flags;
+
+ dma_unmap_sg(mmc_dev(host->mmc), host->sg_ptr, host->sg_len,
+ priv->dma_dir);
+
+ spin_lock_irqsave(&host->lock, flags);
+
+ if (result->result == DMA_TRANS_NOERROR) {
+ /*
+ * When the external DMA engine is enabled, strangely enough,
+ * the DATAEND flag can be asserted even if the DMA engine has
+ * not been kicked yet. Enable the TMIO_STAT_DATAEND irq only
+ * after we make sure the DMA engine finishes the transfer,
+ * hence, in this callback.
+ */
+ tmio_mmc_enable_mmc_irqs(host, TMIO_STAT_DATAEND);
+ } else {
+ host->data->error = -ETIMEDOUT;
+ tmio_mmc_do_data_irq(host);
+ }
+
+ spin_unlock_irqrestore(&host->lock, flags);
+}
+
+static void uniphier_sd_external_dma_start(struct tmio_mmc_host *host,
+ struct mmc_data *data)
+{
+ struct uniphier_sd_priv *priv = uniphier_sd_priv(host);
+ enum dma_transfer_direction dma_tx_dir;
+ struct dma_async_tx_descriptor *desc;
+ dma_cookie_t cookie;
+ int sg_len;
+
+ if (!priv->chan)
+ goto force_pio;
+
+ if (data->flags & MMC_DATA_READ) {
+ priv->dma_dir = DMA_FROM_DEVICE;
+ dma_tx_dir = DMA_DEV_TO_MEM;
+ } else {
+ priv->dma_dir = DMA_TO_DEVICE;
+ dma_tx_dir = DMA_MEM_TO_DEV;
+ }
+
+ sg_len = dma_map_sg(mmc_dev(host->mmc), host->sg_ptr, host->sg_len,
+ priv->dma_dir);
+ if (sg_len == 0)
+ goto force_pio;
+
+ desc = dmaengine_prep_slave_sg(priv->chan, host->sg_ptr, sg_len,
+ dma_tx_dir, DMA_CTRL_ACK);
+ if (!desc)
+ goto unmap_sg;
+
+ desc->callback_result = uniphier_sd_external_dma_callback;
+ desc->callback_param = host;
+
+ cookie = dmaengine_submit(desc);
+ if (cookie < 0)
+ goto unmap_sg;
+
+ return;
+
+unmap_sg:
+ dma_unmap_sg(mmc_dev(host->mmc), host->sg_ptr, host->sg_len,
+ priv->dma_dir);
+force_pio:
+ host->force_pio = true;
+ uniphier_sd_dma_endisable(host, 0);
+}
+
+static void uniphier_sd_external_dma_enable(struct tmio_mmc_host *host,
+ bool enable)
+{
+}
+
+static void uniphier_sd_external_dma_request(struct tmio_mmc_host *host,
+ struct tmio_mmc_data *pdata)
+{
+ struct uniphier_sd_priv *priv = uniphier_sd_priv(host);
+ struct dma_chan *chan;
+
+ chan = dma_request_chan(mmc_dev(host->mmc), "rx-tx");
+ if (IS_ERR(chan)) {
+ dev_warn(mmc_dev(host->mmc),
+ "failed to request DMA channel. falling back to PIO\n");
+ return; /* just use PIO even for -EPROBE_DEFER */
+ }
+
+ /* this driver uses a single channel for both RX an TX */
+ priv->chan = chan;
+ host->chan_rx = chan;
+ host->chan_tx = chan;
+
+ tasklet_init(&host->dma_issue, uniphier_sd_external_dma_issue,
+ (unsigned long)host);
+}
+
+static void uniphier_sd_external_dma_release(struct tmio_mmc_host *host)
+{
+ struct uniphier_sd_priv *priv = uniphier_sd_priv(host);
+
+ if (priv->chan)
+ dma_release_channel(priv->chan);
+}
+
+static void uniphier_sd_external_dma_abort(struct tmio_mmc_host *host)
+{
+ struct uniphier_sd_priv *priv = uniphier_sd_priv(host);
+
+ uniphier_sd_dma_endisable(host, 0);
+
+ if (priv->chan)
+ dmaengine_terminate_sync(priv->chan);
+}
+
+static void uniphier_sd_external_dma_dataend(struct tmio_mmc_host *host)
+{
+ uniphier_sd_dma_endisable(host, 0);
+
+ tmio_mmc_do_data_irq(host);
+}
+
+static const struct tmio_mmc_dma_ops uniphier_sd_external_dma_ops = {
+ .start = uniphier_sd_external_dma_start,
+ .enable = uniphier_sd_external_dma_enable,
+ .request = uniphier_sd_external_dma_request,
+ .release = uniphier_sd_external_dma_release,
+ .abort = uniphier_sd_external_dma_abort,
+ .dataend = uniphier_sd_external_dma_dataend,
+};
+
+static void uniphier_sd_internal_dma_issue(unsigned long arg)
+{
+ struct tmio_mmc_host *host = (void *)arg;
+ unsigned long flags;
+
+ spin_lock_irqsave(&host->lock, flags);
+ tmio_mmc_enable_mmc_irqs(host, TMIO_STAT_DATAEND);
+ spin_unlock_irqrestore(&host->lock, flags);
+
+ uniphier_sd_dma_endisable(host, 1);
+ writel(UNIPHIER_SD_DMA_CTL_START, host->ctl + UNIPHIER_SD_DMA_CTL);
+}
+
+static void uniphier_sd_internal_dma_start(struct tmio_mmc_host *host,
+ struct mmc_data *data)
+{
+ struct uniphier_sd_priv *priv = uniphier_sd_priv(host);
+ struct scatterlist *sg = host->sg_ptr;
+ dma_addr_t dma_addr;
+ unsigned int dma_mode_dir;
+ u32 dma_mode;
+ int sg_len;
+
+ if (WARN_ON(host->sg_len != 1))
+ goto force_pio;
+
+ if (!IS_ALIGNED(sg->offset, 8))
+ goto force_pio;
+
+ if (data->flags & MMC_DATA_READ) {
+ priv->dma_dir = DMA_FROM_DEVICE;
+ dma_mode_dir = UNIPHIER_SD_DMA_MODE_DIR_FROM_DEV;
+ } else {
+ priv->dma_dir = DMA_TO_DEVICE;
+ dma_mode_dir = UNIPHIER_SD_DMA_MODE_DIR_TO_DEV;
+ }
+
+ sg_len = dma_map_sg(mmc_dev(host->mmc), sg, 1, priv->dma_dir);
+ if (sg_len == 0)
+ goto force_pio;
+
+ dma_mode = FIELD_PREP(UNIPHIER_SD_DMA_MODE_DIR_MASK, dma_mode_dir);
+ dma_mode |= FIELD_PREP(UNIPHIER_SD_DMA_MODE_WIDTH_MASK,
+ UNIPHIER_SD_DMA_MODE_WIDTH_64);
+ dma_mode |= UNIPHIER_SD_DMA_MODE_ADDR_INC;
+
+ writel(dma_mode, host->ctl + UNIPHIER_SD_DMA_MODE);
+
+ dma_addr = sg_dma_address(data->sg);
+ writel(lower_32_bits(dma_addr), host->ctl + UNIPHIER_SD_DMA_ADDR_L);
+ writel(upper_32_bits(dma_addr), host->ctl + UNIPHIER_SD_DMA_ADDR_H);
+
+ return;
+force_pio:
+ host->force_pio = true;
+ uniphier_sd_dma_endisable(host, 0);
+}
+
+static void uniphier_sd_internal_dma_enable(struct tmio_mmc_host *host,
+ bool enable)
+{
+}
+
+static void uniphier_sd_internal_dma_request(struct tmio_mmc_host *host,
+ struct tmio_mmc_data *pdata)
+{
+ struct uniphier_sd_priv *priv = uniphier_sd_priv(host);
+
+ /*
+ * Due to a hardware bug, Pro5 cannot use DMA for RX.
+ * We can still use DMA for TX, but PIO for RX.
+ */
+ if (!(priv->caps & UNIPHIER_SD_CAP_BROKEN_DMA_RX))
+ host->chan_rx = (void *)0xdeadbeaf;
+
+ host->chan_tx = (void *)0xdeadbeaf;
+
+ tasklet_init(&host->dma_issue, uniphier_sd_internal_dma_issue,
+ (unsigned long)host);
+}
+
+static void uniphier_sd_internal_dma_release(struct tmio_mmc_host *host)
+{
+ /* Each value is set to zero to assume "disabling" each DMA */
+ host->chan_rx = NULL;
+ host->chan_tx = NULL;
+}
+
+static void uniphier_sd_internal_dma_abort(struct tmio_mmc_host *host)
+{
+ u32 tmp;
+
+ uniphier_sd_dma_endisable(host, 0);
+
+ tmp = readl(host->ctl + UNIPHIER_SD_DMA_RST);
+ tmp &= ~(UNIPHIER_SD_DMA_RST_CH1 | UNIPHIER_SD_DMA_RST_CH0);
+ writel(tmp, host->ctl + UNIPHIER_SD_DMA_RST);
+
+ tmp |= UNIPHIER_SD_DMA_RST_CH1 | UNIPHIER_SD_DMA_RST_CH0;
+ writel(tmp, host->ctl + UNIPHIER_SD_DMA_RST);
+}
+
+static void uniphier_sd_internal_dma_dataend(struct tmio_mmc_host *host)
+{
+ struct uniphier_sd_priv *priv = uniphier_sd_priv(host);
+
+ uniphier_sd_dma_endisable(host, 0);
+ dma_unmap_sg(mmc_dev(host->mmc), host->sg_ptr, 1, priv->dma_dir);
+
+ tmio_mmc_do_data_irq(host);
+}
+
+static const struct tmio_mmc_dma_ops uniphier_sd_internal_dma_ops = {
+ .start = uniphier_sd_internal_dma_start,
+ .enable = uniphier_sd_internal_dma_enable,
+ .request = uniphier_sd_internal_dma_request,
+ .release = uniphier_sd_internal_dma_release,
+ .abort = uniphier_sd_internal_dma_abort,
+ .dataend = uniphier_sd_internal_dma_dataend,
+};
+
+static int uniphier_sd_clk_enable(struct tmio_mmc_host *host)
+{
+ struct uniphier_sd_priv *priv = uniphier_sd_priv(host);
+ struct mmc_host *mmc = host->mmc;
+ int ret;
+
+ ret = clk_prepare_enable(priv->clk);
+ if (ret)
+ return ret;
+
+ ret = clk_set_rate(priv->clk, ULONG_MAX);
+ if (ret)
+ goto disable_clk;
+
+ priv->clk_rate = clk_get_rate(priv->clk);
+
+ /* If max-frequency property is set, use it. */
+ if (!mmc->f_max)
+ mmc->f_max = priv->clk_rate;
+
+ /*
+ * 1/512 is the finest divisor in the original IP. Newer versions
+ * also supports 1/1024 divisor. (UniPhier-specific extension)
+ */
+ if (priv->caps & UNIPHIER_SD_CAP_EXTENDED_IP)
+ mmc->f_min = priv->clk_rate / 1024;
+ else
+ mmc->f_min = priv->clk_rate / 512;
+
+ ret = reset_control_deassert(priv->rst);
+ if (ret)
+ goto disable_clk;
+
+ ret = reset_control_deassert(priv->rst_br);
+ if (ret)
+ goto assert_rst;
+
+ return 0;
+
+assert_rst:
+ reset_control_assert(priv->rst);
+disable_clk:
+ clk_disable_unprepare(priv->clk);
+
+ return ret;
+}
+
+static void uniphier_sd_clk_disable(struct tmio_mmc_host *host)
+{
+ struct uniphier_sd_priv *priv = uniphier_sd_priv(host);
+
+ reset_control_assert(priv->rst_br);
+ reset_control_assert(priv->rst);
+ clk_disable_unprepare(priv->clk);
+}
+
+static void uniphier_sd_hw_reset(struct tmio_mmc_host *host)
+{
+ struct uniphier_sd_priv *priv = uniphier_sd_priv(host);
+
+ reset_control_assert(priv->rst_hw);
+ /* For eMMC, minimum is 1us but give it 9us for good measure */
+ udelay(9);
+ reset_control_deassert(priv->rst_hw);
+ /* For eMMC, minimum is 200us but give it 300us for good measure */
+ usleep_range(300, 1000);
+}
+
+static void uniphier_sd_set_clock(struct tmio_mmc_host *host,
+ unsigned int clock)
+{
+ struct uniphier_sd_priv *priv = uniphier_sd_priv(host);
+ unsigned long divisor;
+ u32 tmp;
+
+ tmp = readl(host->ctl + (CTL_SD_CARD_CLK_CTL << 1));
+
+ /* stop the clock before changing its rate to avoid a glitch signal */
+ tmp &= ~CLK_CTL_SCLKEN;
+ writel(tmp, host->ctl + (CTL_SD_CARD_CLK_CTL << 1));
+
+ if (clock == 0)
+ return;
+
+ tmp &= ~UNIPHIER_SD_CLK_CTL_DIV1024;
+ tmp &= ~UNIPHIER_SD_CLK_CTL_DIV1;
+ tmp &= ~CLK_CTL_DIV_MASK;
+
+ divisor = priv->clk_rate / clock;
+
+ /*
+ * In the original IP, bit[7:0] represents the divisor.
+ * bit7 set: 1/512, ... bit0 set:1/4, all bits clear: 1/2
+ *
+ * The IP does not define a way to achieve 1/1. For UniPhier variants,
+ * bit10 is used for 1/1. Newer versions of UniPhier variants use
+ * bit16 for 1/1024.
+ */
+ if (divisor <= 1)
+ tmp |= UNIPHIER_SD_CLK_CTL_DIV1;
+ else if (priv->caps & UNIPHIER_SD_CAP_EXTENDED_IP && divisor > 512)
+ tmp |= UNIPHIER_SD_CLK_CTL_DIV1024;
+ else
+ tmp |= roundup_pow_of_two(divisor) >> 2;
+
+ writel(tmp, host->ctl + (CTL_SD_CARD_CLK_CTL << 1));
+
+ tmp |= CLK_CTL_SCLKEN;
+ writel(tmp, host->ctl + (CTL_SD_CARD_CLK_CTL << 1));
+}
+
+static void uniphier_sd_host_init(struct tmio_mmc_host *host)
+{
+ struct uniphier_sd_priv *priv = uniphier_sd_priv(host);
+ u32 val;
+
+ /*
+ * Connected to 32bit AXI.
+ * This register holds settings for SoC-specific internal bus
+ * connection. What is worse, the register spec was changed,
+ * breaking the backward compatibility. Write an appropriate
+ * value depending on a flag associated with a compatible string.
+ */
+ if (priv->caps & UNIPHIER_SD_CAP_EXTENDED_IP)
+ val = 0x00000101;
+ else
+ val = 0x00000000;
+
+ writel(val, host->ctl + UNIPHIER_SD_HOST_MODE);
+
+ val = 0;
+ /*
+ * If supported, the controller can automatically
+ * enable/disable the clock line to the card.
+ */
+ if (priv->caps & UNIPHIER_SD_CAP_EXTENDED_IP)
+ val |= UNIPHIER_SD_CLKCTL_OFFEN;
+
+ writel(val, host->ctl + (CTL_SD_CARD_CLK_CTL << 1));
+}
+
+static int uniphier_sd_start_signal_voltage_switch(struct mmc_host *mmc,
+ struct mmc_ios *ios)
+{
+ struct tmio_mmc_host *host = mmc_priv(mmc);
+ struct uniphier_sd_priv *priv = uniphier_sd_priv(host);
+ struct pinctrl_state *pinstate;
+ u32 val, tmp;
+
+ switch (ios->signal_voltage) {
+ case MMC_SIGNAL_VOLTAGE_330:
+ val = UNIPHIER_SD_VOLT_330;
+ pinstate = priv->pinstate_default;
+ break;
+ case MMC_SIGNAL_VOLTAGE_180:
+ val = UNIPHIER_SD_VOLT_180;
+ pinstate = priv->pinstate_uhs;
+ break;
+ default:
+ return -ENOTSUPP;
+ }
+
+ tmp = readl(host->ctl + UNIPHIER_SD_VOLT);
+ tmp &= ~UNIPHIER_SD_VOLT_MASK;
+ tmp |= FIELD_PREP(UNIPHIER_SD_VOLT_MASK, val);
+ writel(tmp, host->ctl + UNIPHIER_SD_VOLT);
+
+ pinctrl_select_state(priv->pinctrl, pinstate);
+
+ return 0;
+}
+
+static int uniphier_sd_uhs_init(struct tmio_mmc_host *host,
+ struct uniphier_sd_priv *priv)
+{
+ priv->pinctrl = devm_pinctrl_get(mmc_dev(host->mmc));
+ if (IS_ERR(priv->pinctrl))
+ return PTR_ERR(priv->pinctrl);
+
+ priv->pinstate_default = pinctrl_lookup_state(priv->pinctrl,
+ PINCTRL_STATE_DEFAULT);
+ if (IS_ERR(priv->pinstate_default))
+ return PTR_ERR(priv->pinstate_default);
+
+ priv->pinstate_uhs = pinctrl_lookup_state(priv->pinctrl, "uhs");
+ if (IS_ERR(priv->pinstate_uhs))
+ return PTR_ERR(priv->pinstate_uhs);
+
+ host->ops.start_signal_voltage_switch =
+ uniphier_sd_start_signal_voltage_switch;
+
+ return 0;
+}
+
+static int uniphier_sd_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct uniphier_sd_priv *priv;
+ struct tmio_mmc_data *tmio_data;
+ struct tmio_mmc_host *host;
+ int irq, ret;
+
+ irq = platform_get_irq(pdev, 0);
+ if (irq < 0) {
+ dev_err(dev, "failed to get IRQ number");
+ return irq;
+ }
+
+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ priv->caps = (unsigned long)of_device_get_match_data(dev);
+
+ priv->clk = devm_clk_get(dev, NULL);
+ if (IS_ERR(priv->clk)) {
+ dev_err(dev, "failed to get clock\n");
+ return PTR_ERR(priv->clk);
+ }
+
+ priv->rst = devm_reset_control_get_shared(dev, "host");
+ if (IS_ERR(priv->rst)) {
+ dev_err(dev, "failed to get host reset\n");
+ return PTR_ERR(priv->rst);
+ }
+
+ /* old version has one more reset */
+ if (!(priv->caps & UNIPHIER_SD_CAP_EXTENDED_IP)) {
+ priv->rst_br = devm_reset_control_get_shared(dev, "bridge");
+ if (IS_ERR(priv->rst_br)) {
+ dev_err(dev, "failed to get bridge reset\n");
+ return PTR_ERR(priv->rst_br);
+ }
+ }
+
+ tmio_data = &priv->tmio_data;
+ tmio_data->flags |= TMIO_MMC_32BIT_DATA_PORT;
+
+ host = tmio_mmc_host_alloc(pdev, tmio_data);
+ if (IS_ERR(host))
+ return PTR_ERR(host);
+
+ if (host->mmc->caps & MMC_CAP_HW_RESET) {
+ priv->rst_hw = devm_reset_control_get_exclusive(dev, "hw");
+ if (IS_ERR(priv->rst_hw)) {
+ dev_err(dev, "failed to get hw reset\n");
+ ret = PTR_ERR(priv->rst_hw);
+ goto free_host;
+ }
+ host->hw_reset = uniphier_sd_hw_reset;
+ }
+
+ if (host->mmc->caps & MMC_CAP_UHS) {
+ ret = uniphier_sd_uhs_init(host, priv);
+ if (ret) {
+ dev_warn(dev,
+ "failed to setup UHS (error %d). Disabling UHS.",
+ ret);
+ host->mmc->caps &= ~MMC_CAP_UHS;
+ }
+ }
+
+ ret = devm_request_irq(dev, irq, tmio_mmc_irq, IRQF_SHARED,
+ dev_name(dev), host);
+ if (ret)
+ goto free_host;
+
+ if (priv->caps & UNIPHIER_SD_CAP_EXTENDED_IP)
+ host->dma_ops = &uniphier_sd_internal_dma_ops;
+ else
+ host->dma_ops = &uniphier_sd_external_dma_ops;
+
+ host->bus_shift = 1;
+ host->clk_enable = uniphier_sd_clk_enable;
+ host->clk_disable = uniphier_sd_clk_disable;
+ host->set_clock = uniphier_sd_set_clock;
+
+ ret = uniphier_sd_clk_enable(host);
+ if (ret)
+ goto free_host;
+
+ uniphier_sd_host_init(host);
+
+ tmio_data->ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34;
+ if (host->mmc->caps & MMC_CAP_UHS)
+ tmio_data->ocr_mask |= MMC_VDD_165_195;
+
+ tmio_data->max_segs = 1;
+ tmio_data->max_blk_count = U16_MAX;
+
+ ret = tmio_mmc_host_probe(host);
+ if (ret)
+ goto free_host;
+
+ return 0;
+
+free_host:
+ tmio_mmc_host_free(host);
+
+ return ret;
+}
+
+static int uniphier_sd_remove(struct platform_device *pdev)
+{
+ struct tmio_mmc_host *host = platform_get_drvdata(pdev);
+
+ tmio_mmc_host_remove(host);
+ uniphier_sd_clk_disable(host);
+
+ return 0;
+}
+
+static const struct of_device_id uniphier_sd_match[] = {
+ {
+ .compatible = "socionext,uniphier-sd-v2.91",
+ },
+ {
+ .compatible = "socionext,uniphier-sd-v3.1",
+ .data = (void *)(UNIPHIER_SD_CAP_EXTENDED_IP |
+ UNIPHIER_SD_CAP_BROKEN_DMA_RX),
+ },
+ {
+ .compatible = "socionext,uniphier-sd-v3.1.1",
+ .data = (void *)UNIPHIER_SD_CAP_EXTENDED_IP,
+ },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, uniphier_sd_match);
+
+static struct platform_driver uniphier_sd_driver = {
+ .probe = uniphier_sd_probe,
+ .remove = uniphier_sd_remove,
+ .driver = {
+ .name = "uniphier-sd",
+ .of_match_table = uniphier_sd_match,
+ },
+};
+module_platform_driver(uniphier_sd_driver);
+
+MODULE_AUTHOR("Masahiro Yamada <yamada.masahiro@socionext.com>");
+MODULE_DESCRIPTION("UniPhier SD/eMMC host controller driver");
+MODULE_LICENSE("GPL v2");
--
2.7.4
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH v3 5/6] mmc: renesas_sdhi: merge clk_{start,stop} functions to set_clock
2018-08-23 4:44 [PATCH v3 0/6] mmc: tmio: refactor TMIO core a bit and add UniPhier SD/eMMC controller support Masahiro Yamada
` (3 preceding siblings ...)
2018-08-23 4:44 ` [PATCH v3 4/6] mmc: uniphier-sd: add UniPhier SD/eMMC controller driver Masahiro Yamada
@ 2018-08-23 4:44 ` Masahiro Yamada
2018-08-29 8:40 ` Wolfram Sang
2018-08-30 12:30 ` Ulf Hansson
2018-08-23 4:44 ` [PATCH v3 6/6] mmc: tmio: refactor CLK_CTL bit calculation Masahiro Yamada
2018-08-23 10:43 ` [PATCH v3 0/6] mmc: tmio: refactor TMIO core a bit and add UniPhier SD/eMMC controller support Ulf Hansson
6 siblings, 2 replies; 18+ messages in thread
From: Masahiro Yamada @ 2018-08-23 4:44 UTC (permalink / raw)
To: Wolfram Sang, linux-mmc
Cc: Ulf Hansson, linux-renesas-soc, Masami Hiramatsu, Jassi Brar,
Masahiro Yamada, linux-kernel
renesas_sdhi_clk_start() and renesas_sdhi_clk_stop() are now only
called from renesas_sdhi_set_clock(). Merge them.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
---
Changes in v3: None
Changes in v2: None
drivers/mmc/host/renesas_sdhi_core.c | 38 ++++++++++++------------------------
1 file changed, 12 insertions(+), 26 deletions(-)
diff --git a/drivers/mmc/host/renesas_sdhi_core.c b/drivers/mmc/host/renesas_sdhi_core.c
index cb6e889..0e88737 100644
--- a/drivers/mmc/host/renesas_sdhi_core.c
+++ b/drivers/mmc/host/renesas_sdhi_core.c
@@ -155,35 +155,17 @@ static unsigned int renesas_sdhi_clk_update(struct tmio_mmc_host *host,
return ret == 0 ? best_freq : clk_get_rate(priv->clk);
}
-static void renesas_sdhi_clk_start(struct tmio_mmc_host *host)
+static void renesas_sdhi_set_clock(struct tmio_mmc_host *host,
+ unsigned int new_clock)
{
- sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
- sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
-
- /* HW engineers overrode docs: no sleep needed on R-Car2+ */
- if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2))
- usleep_range(10000, 11000);
-}
+ u32 clk = 0, clock;
-static void renesas_sdhi_clk_stop(struct tmio_mmc_host *host)
-{
sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
- /* HW engineers overrode docs: no sleep needed on R-Car2+ */
- if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2))
- usleep_range(10000, 11000);
-}
-
-static void renesas_sdhi_set_clock(struct tmio_mmc_host *host,
- unsigned int new_clock)
-{
- u32 clk = 0, clock;
+ if (new_clock == 0)
+ goto out;
- if (new_clock == 0) {
- renesas_sdhi_clk_stop(host);
- return;
- }
/*
* Both HS400 and HS200/SD104 set 200MHz, but some devices need to
* set 400MHz to distinguish the CPG settings in HS400.
@@ -206,13 +188,17 @@ static void renesas_sdhi_set_clock(struct tmio_mmc_host *host,
clk &= ~0xff;
}
- sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
- sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, clk & CLK_CTL_DIV_MASK);
if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2))
usleep_range(10000, 11000);
- renesas_sdhi_clk_start(host);
+ sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
+ sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
+
+out:
+ /* HW engineers overrode docs: no sleep needed on R-Car2+ */
+ if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2))
+ usleep_range(10000, 11000);
}
static void renesas_sdhi_clk_disable(struct tmio_mmc_host *host)
--
2.7.4
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH v3 6/6] mmc: tmio: refactor CLK_CTL bit calculation
2018-08-23 4:44 [PATCH v3 0/6] mmc: tmio: refactor TMIO core a bit and add UniPhier SD/eMMC controller support Masahiro Yamada
` (4 preceding siblings ...)
2018-08-23 4:44 ` [PATCH v3 5/6] mmc: renesas_sdhi: merge clk_{start,stop} functions to set_clock Masahiro Yamada
@ 2018-08-23 4:44 ` Masahiro Yamada
2018-08-29 8:49 ` Wolfram Sang
2018-08-30 12:30 ` Ulf Hansson
2018-08-23 10:43 ` [PATCH v3 0/6] mmc: tmio: refactor TMIO core a bit and add UniPhier SD/eMMC controller support Ulf Hansson
6 siblings, 2 replies; 18+ messages in thread
From: Masahiro Yamada @ 2018-08-23 4:44 UTC (permalink / raw)
To: Wolfram Sang, linux-mmc
Cc: Ulf Hansson, linux-renesas-soc, Masami Hiramatsu, Jassi Brar,
Masahiro Yamada, linux-kernel
for (clk = 0x80000080; new_clock >= (clock << 1); clk >>= 1)
clock <<= 1;
... is too tricky, hence I replaced with
roundup_pow_of_two(divisor) >> 2
'(clk >> 22) & 0x1' is the bit test for the 1/1 divisor, but
it is not clear. 'divisor <= 1' is easier to understand.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
---
Changes in v3: None
Changes in v2: None
drivers/mmc/host/tmio_mmc.c | 18 +++++++++++++-----
1 file changed, 13 insertions(+), 5 deletions(-)
diff --git a/drivers/mmc/host/tmio_mmc.c b/drivers/mmc/host/tmio_mmc.c
index b031a77..e04c322 100644
--- a/drivers/mmc/host/tmio_mmc.c
+++ b/drivers/mmc/host/tmio_mmc.c
@@ -48,19 +48,27 @@ static void tmio_mmc_clk_stop(struct tmio_mmc_host *host)
static void tmio_mmc_set_clock(struct tmio_mmc_host *host,
unsigned int new_clock)
{
- u32 clk = 0, clock;
+ unsigned int clock, divisor;
+ u32 clk = 0;
+ int clk_sel;
if (new_clock == 0) {
tmio_mmc_clk_stop(host);
return;
}
- clock = host->mmc->f_min;
+ divisor = host->pdata->hclk / new_clock;
- for (clk = 0x80000080; new_clock >= (clock << 1); clk >>= 1)
- clock <<= 1;
+ if (divisor <= 1) {
+ clk_sel = 1;
+ clk = 0;
+ } else {
+ clk_sel = 0;
+ /* bit7 set: 1/512, ... bit0 set:1/4, all bits clear: 1/2 */
+ clk = roundup_pow_of_two(divisor) >> 2;
+ }
- host->pdata->set_clk_div(host->pdev, (clk >> 22) & 1);
+ host->pdata->set_clk_div(host->pdev, clk_sel);
sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
--
2.7.4
^ permalink raw reply related [flat|nested] 18+ messages in thread
* Re: [PATCH v3 0/6] mmc: tmio: refactor TMIO core a bit and add UniPhier SD/eMMC controller support
2018-08-23 4:44 [PATCH v3 0/6] mmc: tmio: refactor TMIO core a bit and add UniPhier SD/eMMC controller support Masahiro Yamada
` (5 preceding siblings ...)
2018-08-23 4:44 ` [PATCH v3 6/6] mmc: tmio: refactor CLK_CTL bit calculation Masahiro Yamada
@ 2018-08-23 10:43 ` Ulf Hansson
2018-08-29 8:27 ` Wolfram Sang
6 siblings, 1 reply; 18+ messages in thread
From: Ulf Hansson @ 2018-08-23 10:43 UTC (permalink / raw)
To: Masahiro Yamada
Cc: Wolfram Sang, linux-mmc, Linux-Renesas, Masami Hiramatsu,
Jassi Brar, DTML, Linux Kernel Mailing List, Rob Herring,
Mark Rutland, Linux ARM
On 23 August 2018 at 06:44, Masahiro Yamada
<yamada.masahiro@socionext.com> wrote:
>
> Add UniPhier SD/eMMC controller support.
>
> As a preparation, I changed tmio_mmc_set_clock() to a platform hook.
> The clock rate setting is platform-specific, and UniPhier variants
> will add another way. I thought it would be better to split this
> to a hook to avoid a mess.
>
> V3 is rebase on top of Linus' tree.
I have queued patch 1 -> 4, waiting for further reviews for patch 5 and 6.
One minor comment of patch 4, see separate email.
Kind regards
Uffe
>
> I dropped 6/7 because Renesas added more quirks
> in the current MW.
>
>
> Masahiro Yamada (6):
> mmc: tmio: replace tmio_mmc_clk_stop() calls with tmio_mmc_set_clock()
> mmc: tmio: move tmio_mmc_set_clock() to platform hook
> dt-bindings: mmc: add DT binding for UniPhier SD/eMMC controller
> mmc: uniphier-sd: add UniPhier SD/eMMC controller driver
> mmc: renesas_sdhi: merge clk_{start,stop} functions to set_clock
> mmc: tmio: refactor CLK_CTL bit calculation
>
> .../devicetree/bindings/mmc/uniphier-sd.txt | 55 ++
> MAINTAINERS | 1 +
> drivers/mmc/host/Kconfig | 10 +
> drivers/mmc/host/Makefile | 1 +
> drivers/mmc/host/renesas_sdhi_core.c | 48 +-
> drivers/mmc/host/tmio_mmc.c | 56 ++
> drivers/mmc/host/tmio_mmc.h | 4 +-
> drivers/mmc/host/tmio_mmc_core.c | 92 +--
> drivers/mmc/host/uniphier-sd.c | 693 +++++++++++++++++++++
> 9 files changed, 871 insertions(+), 89 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/mmc/uniphier-sd.txt
> create mode 100644 drivers/mmc/host/uniphier-sd.c
>
> --
> 2.7.4
>
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH v3 4/6] mmc: uniphier-sd: add UniPhier SD/eMMC controller driver
2018-08-23 4:44 ` [PATCH v3 4/6] mmc: uniphier-sd: add UniPhier SD/eMMC controller driver Masahiro Yamada
@ 2018-08-23 10:43 ` Ulf Hansson
2018-08-24 1:50 ` Masahiro Yamada
0 siblings, 1 reply; 18+ messages in thread
From: Ulf Hansson @ 2018-08-23 10:43 UTC (permalink / raw)
To: Masahiro Yamada
Cc: Wolfram Sang, linux-mmc, Linux-Renesas, Masami Hiramatsu,
Jassi Brar, Linux ARM, Linux Kernel Mailing List
[...]
> +static void uniphier_sd_external_dma_request(struct tmio_mmc_host *host,
> + struct tmio_mmc_data *pdata)
> +{
> + struct uniphier_sd_priv *priv = uniphier_sd_priv(host);
> + struct dma_chan *chan;
> +
> + chan = dma_request_chan(mmc_dev(host->mmc), "rx-tx");
> + if (IS_ERR(chan)) {
> + dev_warn(mmc_dev(host->mmc),
> + "failed to request DMA channel. falling back to PIO\n");
> + return; /* just use PIO even for -EPROBE_DEFER */
> + }
> +
> + /* this driver uses a single channel for both RX an TX */
> + priv->chan = chan;
> + host->chan_rx = chan;
> + host->chan_tx = chan;
> +
> + tasklet_init(&host->dma_issue, uniphier_sd_external_dma_issue,
> + (unsigned long)host);
Isn't it time to get rid of tasklets for tmio?
No worries, I don't require that to be changed prior $subject patch,
however using threaded IRQs is a justified modernization for the tmio
variants.
[...]
Kind regards
Uffe
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH v3 4/6] mmc: uniphier-sd: add UniPhier SD/eMMC controller driver
2018-08-23 10:43 ` Ulf Hansson
@ 2018-08-24 1:50 ` Masahiro Yamada
2018-08-24 6:32 ` Ulf Hansson
0 siblings, 1 reply; 18+ messages in thread
From: Masahiro Yamada @ 2018-08-24 1:50 UTC (permalink / raw)
To: Ulf Hansson
Cc: Wolfram Sang, linux-mmc, Linux-Renesas, Masami Hiramatsu,
Jassi Brar, Linux ARM, Linux Kernel Mailing List
2018-08-23 19:43 GMT+09:00 Ulf Hansson <ulf.hansson@linaro.org>:
> [...]
>
>> +static void uniphier_sd_external_dma_request(struct tmio_mmc_host *host,
>> + struct tmio_mmc_data *pdata)
>> +{
>> + struct uniphier_sd_priv *priv = uniphier_sd_priv(host);
>> + struct dma_chan *chan;
>> +
>> + chan = dma_request_chan(mmc_dev(host->mmc), "rx-tx");
>> + if (IS_ERR(chan)) {
>> + dev_warn(mmc_dev(host->mmc),
>> + "failed to request DMA channel. falling back to PIO\n");
>> + return; /* just use PIO even for -EPROBE_DEFER */
>> + }
>> +
>> + /* this driver uses a single channel for both RX an TX */
>> + priv->chan = chan;
>> + host->chan_rx = chan;
>> + host->chan_tx = chan;
>> +
>> + tasklet_init(&host->dma_issue, uniphier_sd_external_dma_issue,
>> + (unsigned long)host);
>
> Isn't it time to get rid of tasklets for tmio?
>
> No worries, I don't require that to be changed prior $subject patch,
> however using threaded IRQs is a justified modernization for the tmio
> variants.
Yeah, I also thought this.
But, the irq handler is in the TMIO common code,
so it would affect Renesas code.
tmio-mmc has lots to be improved.
Tasklet is not the only problem.
Before investing more effort,
I want working code base for my platform.
Anyway, thanks for applying this!
> [...]
>
> Kind regards
> Uffe
--
Best Regards
Masahiro Yamada
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH v3 4/6] mmc: uniphier-sd: add UniPhier SD/eMMC controller driver
2018-08-24 1:50 ` Masahiro Yamada
@ 2018-08-24 6:32 ` Ulf Hansson
0 siblings, 0 replies; 18+ messages in thread
From: Ulf Hansson @ 2018-08-24 6:32 UTC (permalink / raw)
To: Masahiro Yamada
Cc: Wolfram Sang, linux-mmc, Linux-Renesas, Masami Hiramatsu,
Jassi Brar, Linux ARM, Linux Kernel Mailing List
On 24 August 2018 at 03:50, Masahiro Yamada
<yamada.masahiro@socionext.com> wrote:
> 2018-08-23 19:43 GMT+09:00 Ulf Hansson <ulf.hansson@linaro.org>:
>> [...]
>>
>>> +static void uniphier_sd_external_dma_request(struct tmio_mmc_host *host,
>>> + struct tmio_mmc_data *pdata)
>>> +{
>>> + struct uniphier_sd_priv *priv = uniphier_sd_priv(host);
>>> + struct dma_chan *chan;
>>> +
>>> + chan = dma_request_chan(mmc_dev(host->mmc), "rx-tx");
>>> + if (IS_ERR(chan)) {
>>> + dev_warn(mmc_dev(host->mmc),
>>> + "failed to request DMA channel. falling back to PIO\n");
>>> + return; /* just use PIO even for -EPROBE_DEFER */
>>> + }
>>> +
>>> + /* this driver uses a single channel for both RX an TX */
>>> + priv->chan = chan;
>>> + host->chan_rx = chan;
>>> + host->chan_tx = chan;
>>> +
>>> + tasklet_init(&host->dma_issue, uniphier_sd_external_dma_issue,
>>> + (unsigned long)host);
>>
>> Isn't it time to get rid of tasklets for tmio?
>>
>> No worries, I don't require that to be changed prior $subject patch,
>> however using threaded IRQs is a justified modernization for the tmio
>> variants.
>
>
> Yeah, I also thought this.
>
> But, the irq handler is in the TMIO common code,
> so it would affect Renesas code.
Yep.
>
> tmio-mmc has lots to be improved.
> Tasklet is not the only problem.
Sure.
>
>
> Before investing more effort,
> I want working code base for my platform.
Totally acceptable!
[...]
Kind regards
Uffe
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH v3 0/6] mmc: tmio: refactor TMIO core a bit and add UniPhier SD/eMMC controller support
2018-08-23 10:43 ` [PATCH v3 0/6] mmc: tmio: refactor TMIO core a bit and add UniPhier SD/eMMC controller support Ulf Hansson
@ 2018-08-29 8:27 ` Wolfram Sang
0 siblings, 0 replies; 18+ messages in thread
From: Wolfram Sang @ 2018-08-29 8:27 UTC (permalink / raw)
To: Ulf Hansson
Cc: Masahiro Yamada, Wolfram Sang, linux-mmc, Linux-Renesas,
Masami Hiramatsu, Jassi Brar, DTML, Linux Kernel Mailing List,
Rob Herring, Mark Rutland, Linux ARM
[-- Attachment #1: Type: text/plain, Size: 983 bytes --]
On Thu, Aug 23, 2018 at 12:43:31PM +0200, Ulf Hansson wrote:
> On 23 August 2018 at 06:44, Masahiro Yamada
> <yamada.masahiro@socionext.com> wrote:
> >
> > Add UniPhier SD/eMMC controller support.
> >
> > As a preparation, I changed tmio_mmc_set_clock() to a platform hook.
> > The clock rate setting is platform-specific, and UniPhier variants
> > will add another way. I thought it would be better to split this
> > to a hook to avoid a mess.
> >
> > V3 is rebase on top of Linus' tree.
>
> I have queued patch 1 -> 4, waiting for further reviews for patch 5 and 6.
I have re-tested patches 1-4 as applied to mmc/next and it all works
fine. For those
Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Now, going to check patches 5+6...
> > I dropped 6/7 because Renesas added more quirks
> > in the current MW.
Totally fine. We need to cleanup HS400 support more, then we can try the
simplification you did for tmio_mmc.c, too. Thanks!
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH v3 5/6] mmc: renesas_sdhi: merge clk_{start,stop} functions to set_clock
2018-08-23 4:44 ` [PATCH v3 5/6] mmc: renesas_sdhi: merge clk_{start,stop} functions to set_clock Masahiro Yamada
@ 2018-08-29 8:40 ` Wolfram Sang
2018-08-30 12:30 ` Ulf Hansson
1 sibling, 0 replies; 18+ messages in thread
From: Wolfram Sang @ 2018-08-29 8:40 UTC (permalink / raw)
To: Masahiro Yamada
Cc: Wolfram Sang, linux-mmc, Ulf Hansson, linux-renesas-soc,
Masami Hiramatsu, Jassi Brar, linux-kernel
[-- Attachment #1: Type: text/plain, Size: 471 bytes --]
On Thu, Aug 23, 2018 at 01:44:19PM +0900, Masahiro Yamada wrote:
> renesas_sdhi_clk_start() and renesas_sdhi_clk_stop() are now only
> called from renesas_sdhi_set_clock(). Merge them.
>
> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Nice cleanup, works fine, and I don't see any issues with the
datasheets. Thanks!
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH v3 6/6] mmc: tmio: refactor CLK_CTL bit calculation
2018-08-23 4:44 ` [PATCH v3 6/6] mmc: tmio: refactor CLK_CTL bit calculation Masahiro Yamada
@ 2018-08-29 8:49 ` Wolfram Sang
2018-08-30 11:51 ` Ulf Hansson
2018-08-30 12:30 ` Ulf Hansson
1 sibling, 1 reply; 18+ messages in thread
From: Wolfram Sang @ 2018-08-29 8:49 UTC (permalink / raw)
To: Masahiro Yamada
Cc: Wolfram Sang, linux-mmc, Ulf Hansson, linux-renesas-soc,
Masami Hiramatsu, Jassi Brar, linux-kernel
[-- Attachment #1: Type: text/plain, Size: 378 bytes --]
> + if (divisor <= 1) {
> + clk_sel = 1;
> + clk = 0;
> + } else {
> + clk_sel = 0;
> + /* bit7 set: 1/512, ... bit0 set:1/4, all bits clear: 1/2 */
> + clk = roundup_pow_of_two(divisor) >> 2;
> + }
What about
clk_sel = (divisor <= 1);
clk = clk_sel ? 0 : (roundup_pow_of_two(divisor) >> 2)
More concise, but I think still readable. I don't mind super much,
though.
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH v3 6/6] mmc: tmio: refactor CLK_CTL bit calculation
2018-08-29 8:49 ` Wolfram Sang
@ 2018-08-30 11:51 ` Ulf Hansson
2018-08-30 12:03 ` Wolfram Sang
0 siblings, 1 reply; 18+ messages in thread
From: Ulf Hansson @ 2018-08-30 11:51 UTC (permalink / raw)
To: Wolfram Sang
Cc: Masahiro Yamada, Wolfram Sang, linux-mmc, Linux-Renesas,
Masami Hiramatsu, Jassi Brar, Linux Kernel Mailing List
On 29 August 2018 at 10:49, Wolfram Sang <wsa@the-dreams.de> wrote:
>
>> + if (divisor <= 1) {
>> + clk_sel = 1;
>> + clk = 0;
>> + } else {
>> + clk_sel = 0;
>> + /* bit7 set: 1/512, ... bit0 set:1/4, all bits clear: 1/2 */
>> + clk = roundup_pow_of_two(divisor) >> 2;
>> + }
>
> What about
>
> clk_sel = (divisor <= 1);
> clk = clk_sel ? 0 : (roundup_pow_of_two(divisor) >> 2)
>
> More concise, but I think still readable. I don't mind super much,
> though.
Right. So, may I apply Yamada-san's original patch (adding your
tested/reviewed-by tag) and the above as a code-cleanup for you to
address on top?
Kind regards
Uffe
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH v3 6/6] mmc: tmio: refactor CLK_CTL bit calculation
2018-08-30 11:51 ` Ulf Hansson
@ 2018-08-30 12:03 ` Wolfram Sang
0 siblings, 0 replies; 18+ messages in thread
From: Wolfram Sang @ 2018-08-30 12:03 UTC (permalink / raw)
To: Ulf Hansson
Cc: Masahiro Yamada, Wolfram Sang, linux-mmc, Linux-Renesas,
Masami Hiramatsu, Jassi Brar, Linux Kernel Mailing List
[-- Attachment #1: Type: text/plain, Size: 912 bytes --]
On Thu, Aug 30, 2018 at 01:51:49PM +0200, Ulf Hansson wrote:
> On 29 August 2018 at 10:49, Wolfram Sang <wsa@the-dreams.de> wrote:
> >
> >> + if (divisor <= 1) {
> >> + clk_sel = 1;
> >> + clk = 0;
> >> + } else {
> >> + clk_sel = 0;
> >> + /* bit7 set: 1/512, ... bit0 set:1/4, all bits clear: 1/2 */
> >> + clk = roundup_pow_of_two(divisor) >> 2;
> >> + }
> >
> > What about
> >
> > clk_sel = (divisor <= 1);
> > clk = clk_sel ? 0 : (roundup_pow_of_two(divisor) >> 2)
> >
> > More concise, but I think still readable. I don't mind super much,
> > though.
>
> Right. So, may I apply Yamada-san's original patch (adding your
> tested/reviewed-by tag) and the above as a code-cleanup for you to
> address on top?
I can resend this as a proper patch if you prefer it to be handled
incrementally.
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH v3 5/6] mmc: renesas_sdhi: merge clk_{start,stop} functions to set_clock
2018-08-23 4:44 ` [PATCH v3 5/6] mmc: renesas_sdhi: merge clk_{start,stop} functions to set_clock Masahiro Yamada
2018-08-29 8:40 ` Wolfram Sang
@ 2018-08-30 12:30 ` Ulf Hansson
1 sibling, 0 replies; 18+ messages in thread
From: Ulf Hansson @ 2018-08-30 12:30 UTC (permalink / raw)
To: Masahiro Yamada
Cc: Wolfram Sang, linux-mmc, Linux-Renesas, Masami Hiramatsu,
Jassi Brar, Linux Kernel Mailing List
On 23 August 2018 at 06:44, Masahiro Yamada
<yamada.masahiro@socionext.com> wrote:
> renesas_sdhi_clk_start() and renesas_sdhi_clk_stop() are now only
> called from renesas_sdhi_set_clock(). Merge them.
>
> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Applied for next, thanks!
Kind regards
Uffe
> ---
>
> Changes in v3: None
> Changes in v2: None
>
> drivers/mmc/host/renesas_sdhi_core.c | 38 ++++++++++++------------------------
> 1 file changed, 12 insertions(+), 26 deletions(-)
>
> diff --git a/drivers/mmc/host/renesas_sdhi_core.c b/drivers/mmc/host/renesas_sdhi_core.c
> index cb6e889..0e88737 100644
> --- a/drivers/mmc/host/renesas_sdhi_core.c
> +++ b/drivers/mmc/host/renesas_sdhi_core.c
> @@ -155,35 +155,17 @@ static unsigned int renesas_sdhi_clk_update(struct tmio_mmc_host *host,
> return ret == 0 ? best_freq : clk_get_rate(priv->clk);
> }
>
> -static void renesas_sdhi_clk_start(struct tmio_mmc_host *host)
> +static void renesas_sdhi_set_clock(struct tmio_mmc_host *host,
> + unsigned int new_clock)
> {
> - sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
> - sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
> -
> - /* HW engineers overrode docs: no sleep needed on R-Car2+ */
> - if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2))
> - usleep_range(10000, 11000);
> -}
> + u32 clk = 0, clock;
>
> -static void renesas_sdhi_clk_stop(struct tmio_mmc_host *host)
> -{
> sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
> sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
>
> - /* HW engineers overrode docs: no sleep needed on R-Car2+ */
> - if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2))
> - usleep_range(10000, 11000);
> -}
> -
> -static void renesas_sdhi_set_clock(struct tmio_mmc_host *host,
> - unsigned int new_clock)
> -{
> - u32 clk = 0, clock;
> + if (new_clock == 0)
> + goto out;
>
> - if (new_clock == 0) {
> - renesas_sdhi_clk_stop(host);
> - return;
> - }
> /*
> * Both HS400 and HS200/SD104 set 200MHz, but some devices need to
> * set 400MHz to distinguish the CPG settings in HS400.
> @@ -206,13 +188,17 @@ static void renesas_sdhi_set_clock(struct tmio_mmc_host *host,
> clk &= ~0xff;
> }
>
> - sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
> - sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
> sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, clk & CLK_CTL_DIV_MASK);
> if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2))
> usleep_range(10000, 11000);
>
> - renesas_sdhi_clk_start(host);
> + sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
> + sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
> +
> +out:
> + /* HW engineers overrode docs: no sleep needed on R-Car2+ */
> + if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2))
> + usleep_range(10000, 11000);
> }
>
> static void renesas_sdhi_clk_disable(struct tmio_mmc_host *host)
> --
> 2.7.4
>
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH v3 6/6] mmc: tmio: refactor CLK_CTL bit calculation
2018-08-23 4:44 ` [PATCH v3 6/6] mmc: tmio: refactor CLK_CTL bit calculation Masahiro Yamada
2018-08-29 8:49 ` Wolfram Sang
@ 2018-08-30 12:30 ` Ulf Hansson
1 sibling, 0 replies; 18+ messages in thread
From: Ulf Hansson @ 2018-08-30 12:30 UTC (permalink / raw)
To: Masahiro Yamada
Cc: Wolfram Sang, linux-mmc, Linux-Renesas, Masami Hiramatsu,
Jassi Brar, Linux Kernel Mailing List
On 23 August 2018 at 06:44, Masahiro Yamada
<yamada.masahiro@socionext.com> wrote:
> for (clk = 0x80000080; new_clock >= (clock << 1); clk >>= 1)
> clock <<= 1;
>
> ... is too tricky, hence I replaced with
>
> roundup_pow_of_two(divisor) >> 2
>
> '(clk >> 22) & 0x1' is the bit test for the 1/1 divisor, but
> it is not clear. 'divisor <= 1' is easier to understand.
>
> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Applied for next, thanks!
Kind regards
Uffe
> ---
>
> Changes in v3: None
> Changes in v2: None
>
> drivers/mmc/host/tmio_mmc.c | 18 +++++++++++++-----
> 1 file changed, 13 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/mmc/host/tmio_mmc.c b/drivers/mmc/host/tmio_mmc.c
> index b031a77..e04c322 100644
> --- a/drivers/mmc/host/tmio_mmc.c
> +++ b/drivers/mmc/host/tmio_mmc.c
> @@ -48,19 +48,27 @@ static void tmio_mmc_clk_stop(struct tmio_mmc_host *host)
> static void tmio_mmc_set_clock(struct tmio_mmc_host *host,
> unsigned int new_clock)
> {
> - u32 clk = 0, clock;
> + unsigned int clock, divisor;
> + u32 clk = 0;
> + int clk_sel;
>
> if (new_clock == 0) {
> tmio_mmc_clk_stop(host);
> return;
> }
>
> - clock = host->mmc->f_min;
> + divisor = host->pdata->hclk / new_clock;
>
> - for (clk = 0x80000080; new_clock >= (clock << 1); clk >>= 1)
> - clock <<= 1;
> + if (divisor <= 1) {
> + clk_sel = 1;
> + clk = 0;
> + } else {
> + clk_sel = 0;
> + /* bit7 set: 1/512, ... bit0 set:1/4, all bits clear: 1/2 */
> + clk = roundup_pow_of_two(divisor) >> 2;
> + }
>
> - host->pdata->set_clk_div(host->pdev, (clk >> 22) & 1);
> + host->pdata->set_clk_div(host->pdev, clk_sel);
>
> sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
> sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
> --
> 2.7.4
>
^ permalink raw reply [flat|nested] 18+ messages in thread
end of thread, other threads:[~2018-08-30 12:30 UTC | newest]
Thread overview: 18+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-08-23 4:44 [PATCH v3 0/6] mmc: tmio: refactor TMIO core a bit and add UniPhier SD/eMMC controller support Masahiro Yamada
2018-08-23 4:44 ` [PATCH v3 1/6] mmc: tmio: replace tmio_mmc_clk_stop() calls with tmio_mmc_set_clock() Masahiro Yamada
2018-08-23 4:44 ` [PATCH v3 2/6] mmc: tmio: move tmio_mmc_set_clock() to platform hook Masahiro Yamada
2018-08-23 4:44 ` [PATCH v3 3/6] dt-bindings: mmc: add DT binding for UniPhier SD/eMMC controller Masahiro Yamada
2018-08-23 4:44 ` [PATCH v3 4/6] mmc: uniphier-sd: add UniPhier SD/eMMC controller driver Masahiro Yamada
2018-08-23 10:43 ` Ulf Hansson
2018-08-24 1:50 ` Masahiro Yamada
2018-08-24 6:32 ` Ulf Hansson
2018-08-23 4:44 ` [PATCH v3 5/6] mmc: renesas_sdhi: merge clk_{start,stop} functions to set_clock Masahiro Yamada
2018-08-29 8:40 ` Wolfram Sang
2018-08-30 12:30 ` Ulf Hansson
2018-08-23 4:44 ` [PATCH v3 6/6] mmc: tmio: refactor CLK_CTL bit calculation Masahiro Yamada
2018-08-29 8:49 ` Wolfram Sang
2018-08-30 11:51 ` Ulf Hansson
2018-08-30 12:03 ` Wolfram Sang
2018-08-30 12:30 ` Ulf Hansson
2018-08-23 10:43 ` [PATCH v3 0/6] mmc: tmio: refactor TMIO core a bit and add UniPhier SD/eMMC controller support Ulf Hansson
2018-08-29 8:27 ` Wolfram Sang
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).