* [PATCH 10/14] dt-bindings: pinctrl: milbeaut: Add Milbeaut M10V pinctrl description
@ 2018-11-19 1:02 Sugaya Taichi
2018-11-19 1:02 ` [PATCH 11/14] pinctrl: milbeaut: Add Milbeaut M10V pinctrl Sugaya Taichi
` (4 more replies)
0 siblings, 5 replies; 11+ messages in thread
From: Sugaya Taichi @ 2018-11-19 1:02 UTC (permalink / raw)
To: linux-clk, devicetree, linux-arm-kernel, linux-kernel, linux-serial
Cc: Michael Turquette, Stephen Boyd, Rob Herring, Mark Rutland,
Greg Kroah-Hartman, Daniel Lezcano, Thomas Gleixner,
Russell King, Jiri Slaby, Masami Hiramatsu, Jassi Brar,
Sugaya Taichi
Add DT bindings document for Milbeaut M10V pinctrl.
Signed-off-by: Sugaya Taichi <sugaya.taichi@socionext.com>
---
.../pinctrl/socionext,milbeaut-pinctrl.txt | 33 ++++++++++++++++++++++
1 file changed, 33 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pinctrl/socionext,milbeaut-pinctrl.txt
diff --git a/Documentation/devicetree/bindings/pinctrl/socionext,milbeaut-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/socionext,milbeaut-pinctrl.txt
new file mode 100644
index 0000000..7469189
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/socionext,milbeaut-pinctrl.txt
@@ -0,0 +1,33 @@
+Milbeaut SoCs pin controller
+
+Required properties:
+- compatible: should be one of the following:
+ "socionext,milbeaut-m10v-pinctrl" - for m10v SoC
+- reg: offset and length of the register set.
+- reg-names: should be "pinctrl", "exiu".
+- gpio-cells; should be 2.
+- interrupt-cells: should be 2.
+- clocks: phandle to the input clock.
+- interrupts: three interrupts specifer.
+- interrupt-names: corresponds "interrupts" factor.
+
+Example:
+ pinctrl: pinctrl@1d022000 {
+ compatible = "socionext,milbeaut-m10v-pinctrl";
+ reg = <0x1d022000 0x1000>,
+ <0x1c26f000 0x1000>;
+ reg-names = "pinctrl", "exiu";
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&dummy_clk>;
+ interrupts = <0 54 4>, <0 55 4>, <0 56 4>, <0 57 4>,
+ <0 58 4>, <0 59 4>, <0 60 4>, <0 61 4>,
+ <0 62 4>, <0 63 4>, <0 64 4>, <0 65 4>,
+ <0 66 4>, <0 67 4>, <0 68 4>, <0 69 4>;
+ interrupt-names = "pin-48", "pin-49", "pin-50", "pin-51",
+ "pin-52", "pin-53", "pin-54", "pin-55",
+ "pin-56", "pin-57", "pin-58", "pin-59",
+ "pin-60", "pin-61", "pin-62", "pin-63";
+ }
--
1.9.1
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH 11/14] pinctrl: milbeaut: Add Milbeaut M10V pinctrl
2018-11-19 1:02 [PATCH 10/14] dt-bindings: pinctrl: milbeaut: Add Milbeaut M10V pinctrl description Sugaya Taichi
@ 2018-11-19 1:02 ` Sugaya Taichi
2018-12-04 11:23 ` Masahiro Yamada
2018-11-19 1:02 ` [PATCH 12/14] ARM: dts: milbeaut: Add device tree set for the Milbeaut M10V board Sugaya Taichi
` (3 subsequent siblings)
4 siblings, 1 reply; 11+ messages in thread
From: Sugaya Taichi @ 2018-11-19 1:02 UTC (permalink / raw)
To: linux-clk, devicetree, linux-arm-kernel, linux-kernel, linux-serial
Cc: Michael Turquette, Stephen Boyd, Rob Herring, Mark Rutland,
Greg Kroah-Hartman, Daniel Lezcano, Thomas Gleixner,
Russell King, Jiri Slaby, Masami Hiramatsu, Jassi Brar,
Sugaya Taichi
Add Milbeaut M10V pinctrl.
The M10V has the pins that can be used GPIOs or take multiple other
functions.
Signed-off-by: Sugaya Taichi <sugaya.taichi@socionext.com>
---
drivers/pinctrl/Kconfig | 9 +
drivers/pinctrl/Makefile | 1 +
drivers/pinctrl/pinctrl-m10v.c | 765 +++++++++++++++++++++++++++++++++++++++++
3 files changed, 775 insertions(+)
create mode 100644 drivers/pinctrl/pinctrl-m10v.c
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 4d8c00e..b9f17e0 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -177,6 +177,15 @@ config PINCTRL_OXNAS
select GPIOLIB_IRQCHIP
select MFD_SYSCON
+config PINCTRL_M10V
+ bool
+ select PINMUX
+ select PINCONF
+ select GENERIC_PINCONF
+ select OF_GPIO
+ select REGMAP_MMIO
+ select GPIOLIB_IRQCHIP
+
config PINCTRL_ROCKCHIP
bool
select PINMUX
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index 18a13c1..1a4a2b2 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -21,6 +21,7 @@ obj-$(CONFIG_PINCTRL_GEMINI) += pinctrl-gemini.o
obj-$(CONFIG_PINCTRL_MAX77620) += pinctrl-max77620.o
obj-$(CONFIG_PINCTRL_MCP23S08) += pinctrl-mcp23s08.o
obj-$(CONFIG_PINCTRL_MESON) += meson/
+obj-$(CONFIG_PINCTRL_M10V) += pinctrl-m10v.o
obj-$(CONFIG_PINCTRL_OXNAS) += pinctrl-oxnas.o
obj-$(CONFIG_PINCTRL_PALMAS) += pinctrl-palmas.o
obj-$(CONFIG_PINCTRL_PIC32) += pinctrl-pic32.o
diff --git a/drivers/pinctrl/pinctrl-m10v.c b/drivers/pinctrl/pinctrl-m10v.c
new file mode 100644
index 0000000..d4ca713
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-m10v.c
@@ -0,0 +1,765 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018 Socionext Ltd.
+ * Copyright (C) 2015 Linaro Ltd.
+ * Author: Jassi Brar <jaswinder.singh@linaro.org>
+ */
+
+#include <linux/gpio.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/of_irq.h>
+#include <linux/pinctrl/machine.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/pinctrl/pinmux.h>
+#include <linux/pinctrl/pinconf.h>
+#include <linux/pinctrl/pinconf-generic.h>
+#include <linux/platform_device.h>
+#include <linux/spinlock.h>
+
+#include "pinctrl-utils.h"
+
+#define EIMASK 0x0
+#define EISRCSEL 0x4
+#define EIREQSTA 0x8
+#define EIRAWREQSTA 0xc
+#define EIREQCLR 0x10
+#define EILVL 0x14
+#define EIEDG 0x18
+#define EISIR 0x1c
+
+#define PDR 0x0
+#define PDR_S 0x50
+#define PDR_C 0xa0
+#define DDR 0x100
+#define EPCR 0x200
+#define PUDER 0x300
+#define PUDCR 0x400
+
+#define M10V_BANKS 26
+#define PINS_PER_BANK 8
+#define M10V_TOTAL_PINS (M10V_BANKS * PINS_PER_BANK)
+#define PINS_PER_REG 16
+
+struct pin_irq_map {
+ int pin; /* offset of pin in the managed range */
+ int irq; /* virq of the pin as fpint */
+ int type;
+ char irqname[8];
+};
+
+struct m10v_pinctrl {
+ void __iomem *base;
+ void __iomem *exiu;
+ struct gpio_chip gc;
+ struct pinctrl_desc pd;
+ char pin_names[4 * M10V_TOTAL_PINS];
+ struct pinctrl_pin_desc pins[M10V_TOTAL_PINS];
+ unsigned int gpins[M10V_TOTAL_PINS][1]; /* 1 pin-per-group */
+ struct irq_domain *irqdom;
+ spinlock_t irq_lock, lock;
+ int extints;
+ struct pin_irq_map fpint[]; /* keep at end */
+};
+
+struct milbeaut_function {
+ const char *name;
+ const char * const *groups;
+ unsigned int ngroups;
+};
+
+static const char m10v_bank_name[] = {'0', '1', '2', '3', '4', '5', '6', '7',
+ '8', '9', 'A', 'B', 'C', 'D', 'E', 'F',
+ 'G', 'H', 'W', 'J', 'K', 'L', 'M', 'N',
+ 'Y', 'P'};
+static const char * const usio0_m10v_grps[] = {"PE2", "PE3", "PF0"};
+static const char * const usio1_m10v_grps[] = {"PE4", "PE5", "PF1"};
+static const char * const usio2_m10v_grps[] = {"PE0", "PE1"};
+static const char * const usio3_m10v_grps[] = {"PY0", "PY1", "PY2"};
+static const char * const usio4_m10v_grps[] = {"PP0", "PP1", "PP2"};
+static const char * const usio5_m10v_grps[] = {"PM0", "PM1", "PM3"};
+static const char * const usio6_m10v_grps[] = {"PN0", "PN1", "PN3"};
+static const char * const usio7_m10v_grps[] = {"PY3", "PY5", "PY6"};
+static const char *gpio_m10v_grps[M10V_TOTAL_PINS];
+
+static const struct milbeaut_function m10v_functions[] = {
+#define FUNC_M10V(fname) \
+ { \
+ .name = #fname, \
+ .groups = fname##_m10v_grps, \
+ .ngroups = ARRAY_SIZE(fname##_m10v_grps), \
+ }
+ FUNC_M10V(gpio), /* GPIO always at index 0 */
+ FUNC_M10V(usio0),
+ FUNC_M10V(usio1),
+ FUNC_M10V(usio2),
+ FUNC_M10V(usio3),
+ FUNC_M10V(usio4),
+ FUNC_M10V(usio5),
+ FUNC_M10V(usio6),
+ FUNC_M10V(usio7),
+};
+
+static const char *bank_name;
+static const struct milbeaut_function *milbeaut_functions;
+
+static int m10v_pconf_group_set(struct pinctrl_dev *pctldev,
+ unsigned int group,
+ unsigned long *configs,
+ unsigned int num_configs)
+{
+ struct m10v_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+ u32 pin, val, reg, offset;
+ unsigned long flags;
+ int i;
+
+ pin = pctl->gpins[group][0];
+ reg = pin / PINS_PER_REG * 4;
+ offset = pin % PINS_PER_REG;
+
+ spin_lock_irqsave(&pctl->lock, flags);
+
+ for (i = 0; i < num_configs; i++) {
+ switch (pinconf_to_config_param(configs[i])) {
+ case PIN_CONFIG_BIAS_PULL_UP:
+ /* enable Pull-Up/Down resistance */
+ val = readl_relaxed(pctl->base + PUDER + reg);
+ val |= BIT(offset);
+ writel_relaxed(val, pctl->base + PUDER + reg);
+ /* enable Pull-Up */
+ val = readl_relaxed(pctl->base + PUDCR + reg);
+ val |= BIT(offset);
+ writel_relaxed(val, pctl->base + PUDCR + reg);
+ break;
+ case PIN_CONFIG_BIAS_PULL_DOWN:
+ /* enable Pull-Up/Down resistance */
+ val = readl_relaxed(pctl->base + PUDER + reg);
+ val |= BIT(offset);
+ writel_relaxed(val, pctl->base + PUDER + reg);
+ /* enable Pull-Down */
+ val = readl_relaxed(pctl->base + PUDCR + reg);
+ val &= ~BIT(offset);
+ writel_relaxed(val, pctl->base + PUDCR + reg);
+ break;
+ case PIN_CONFIG_BIAS_DISABLE:
+ val = readl_relaxed(pctl->base + PUDER + reg);
+ val &= ~BIT(offset);
+ writel_relaxed(val, pctl->base + PUDER + reg);
+ break;
+ default:
+ break;
+ }
+ }
+
+ spin_unlock_irqrestore(&pctl->lock, flags);
+
+ return 0;
+}
+
+static const struct pinconf_ops m10v_pconf_ops = {
+ .pin_config_group_set = m10v_pconf_group_set,
+};
+
+static int m10v_pctrl_get_groups_count(struct pinctrl_dev *pctldev)
+{
+ return M10V_TOTAL_PINS;
+}
+
+static const char *m10v_pctrl_get_group_name(struct pinctrl_dev *pctldev,
+ unsigned int pin)
+{
+ struct m10v_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+
+ return &pctl->pin_names[4 * pin];
+}
+
+static int m10v_pctrl_get_group_pins(struct pinctrl_dev *pctldev,
+ unsigned int group,
+ const unsigned int **pins,
+ unsigned int *num_pins)
+{
+ struct m10v_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+
+ *pins = pctl->gpins[group];
+ *num_pins = 1;
+ return 0;
+}
+
+static const struct pinctrl_ops m10v_pctrl_ops = {
+ .get_groups_count = m10v_pctrl_get_groups_count,
+ .get_group_name = m10v_pctrl_get_group_name,
+ .get_group_pins = m10v_pctrl_get_group_pins,
+ .dt_node_to_map = pinconf_generic_dt_node_to_map_group,
+ .dt_free_map = pinctrl_utils_free_map,
+};
+
+static int m10v_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev)
+{
+ return ARRAY_SIZE(m10v_functions);
+}
+
+static const char *m10v_pmx_get_func_name(struct pinctrl_dev *pctldev,
+ unsigned int function)
+{
+ return milbeaut_functions[function].name;
+}
+
+static int m10v_pmx_get_func_groups(struct pinctrl_dev *pctldev,
+ unsigned int function,
+ const char * const **groups,
+ unsigned * const num_groups)
+{
+ *groups = milbeaut_functions[function].groups;
+ *num_groups = milbeaut_functions[function].ngroups;
+ return 0;
+}
+
+static void _set_mux(struct m10v_pinctrl *pctl, unsigned int pin, bool gpio)
+{
+ u32 val, reg, offset;
+ unsigned long flags;
+
+ reg = pin / PINS_PER_REG * 4;
+ offset = pin % PINS_PER_REG;
+
+ reg += EPCR;
+
+ spin_lock_irqsave(&pctl->lock, flags);
+
+ val = readl_relaxed(pctl->base + reg);
+
+ if (gpio)
+ val &= ~BIT(offset);
+ else
+ val |= BIT(offset);
+
+ writel_relaxed(val, pctl->base + reg);
+
+ spin_unlock_irqrestore(&pctl->lock, flags);
+}
+
+static int m10v_pmx_set_mux(struct pinctrl_dev *pctldev,
+ unsigned int function,
+ unsigned int group)
+{
+ struct m10v_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+ u32 pin = pctl->gpins[group][0]; /* each group has exactly 1 pin */
+
+ _set_mux(pctl, pin, !function);
+
+ return 0;
+}
+
+static int _set_direction(struct m10v_pinctrl *pctl,
+ unsigned int pin, bool input)
+{
+ u32 val, reg, offset;
+ unsigned long flags;
+
+ reg = pin / PINS_PER_REG * 4;
+ offset = pin % PINS_PER_REG;
+
+ reg += DDR;
+
+ spin_lock_irqsave(&pctl->lock, flags);
+
+ val = readl_relaxed(pctl->base + reg);
+
+ if (input)
+ val &= ~BIT(offset);
+ else
+ val |= BIT(offset);
+
+ writel_relaxed(val, pctl->base + reg);
+
+ spin_unlock_irqrestore(&pctl->lock, flags);
+
+ return 0;
+}
+
+static int
+m10v_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
+ struct pinctrl_gpio_range *range,
+ unsigned int pin, bool input)
+{
+ struct m10v_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+
+ return _set_direction(pctl, pin, input);
+}
+
+static int
+m10v_pmx_gpio_request_enable(struct pinctrl_dev *pctldev,
+ struct pinctrl_gpio_range *range,
+ unsigned int pin)
+{
+ struct m10v_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+
+ _set_mux(pctl, pin, true);
+ return 0;
+}
+
+static const struct pinmux_ops m10v_pmx_ops = {
+ .get_functions_count = m10v_pmx_get_funcs_cnt,
+ .get_function_name = m10v_pmx_get_func_name,
+ .get_function_groups = m10v_pmx_get_func_groups,
+ .set_mux = m10v_pmx_set_mux,
+ .gpio_set_direction = m10v_pmx_gpio_set_direction,
+ .gpio_request_enable = m10v_pmx_gpio_request_enable,
+};
+
+static int m10v_gpio_get(struct gpio_chip *gc, unsigned int group)
+{
+ struct m10v_pinctrl *pctl =
+ container_of(gc, struct m10v_pinctrl, gc);
+ u32 pin, val, reg, offset;
+
+ pin = pctl->gpins[group][0];
+ reg = PDR + pin / PINS_PER_REG * 4;
+ offset = pin % PINS_PER_REG;
+ val = readl_relaxed(pctl->base + reg);
+
+ return !!(val & BIT(offset));
+}
+
+static void m10v_gpio_set(struct gpio_chip *gc, unsigned int group, int set)
+{
+ struct m10v_pinctrl *pctl =
+ container_of(gc, struct m10v_pinctrl, gc);
+ u32 pin, reg, offset, val;
+
+ pin = pctl->gpins[group][0];
+ reg = PDR + pin / PINS_PER_REG * 4;
+ offset = pin % PINS_PER_REG;
+
+ val = BIT(offset + 16);
+ if (set)
+ val |= BIT(offset);
+
+ writel_relaxed(val, pctl->base + reg);
+}
+
+static void (*gpio_set)(struct gpio_chip *, unsigned int, int);
+
+static int m10v_gpio_direction_input(struct gpio_chip *gc,
+ unsigned int offset)
+{
+ return pinctrl_gpio_direction_input(gc->base + offset);
+}
+
+static int m10v_gpio_direction_output(struct gpio_chip *gc,
+ unsigned int offset, int value)
+{
+ int ret;
+
+ ret = pinctrl_gpio_direction_output(gc->base + offset);
+ if (!ret)
+ gpio_set(gc, offset, value);
+
+ return ret;
+}
+
+static int m10v_gpio_to_irq(struct gpio_chip *gc, unsigned int offset)
+{
+ struct m10v_pinctrl *pctl =
+ container_of(gc, struct m10v_pinctrl, gc);
+
+ return irq_linear_revmap(pctl->irqdom, offset);
+}
+
+static struct lock_class_key gpio_lock_class;
+static struct lock_class_key gpio_request_class;
+
+static int pin_to_extint(struct m10v_pinctrl *pctl, int pin)
+{
+ int extint;
+
+ for (extint = 0; extint < pctl->extints; extint++)
+ if (pctl->fpint[extint].pin == pin)
+ break;
+
+ if (extint == pctl->extints)
+ return -1;
+
+ return extint;
+}
+
+static void update_trigger(struct m10v_pinctrl *pctl, int extint)
+{
+ int type = pctl->fpint[extint].type;
+ int pin = pctl->fpint[extint].pin;
+ u32 masked, val, eilvl, eiedg;
+ int lvl;
+ u32 reg, offset;
+
+ reg = pin / PINS_PER_REG * 4;
+ offset = pin % PINS_PER_REG;
+
+ /* sense gpio */
+ val = readl_relaxed(pctl->base + PDR + reg);
+ lvl = (val >> offset) & 1;
+
+ eilvl = readl_relaxed(pctl->exiu + EILVL);
+ eiedg = readl_relaxed(pctl->exiu + EIEDG);
+
+ if (type == IRQ_TYPE_LEVEL_LOW ||
+ (lvl && (type & IRQ_TYPE_LEVEL_LOW))) {
+ eilvl &= ~BIT(extint);
+ eiedg &= ~BIT(extint);
+ }
+
+ if (type == IRQ_TYPE_EDGE_FALLING ||
+ (lvl && (type & IRQ_TYPE_EDGE_FALLING))) {
+ eilvl &= ~BIT(extint);
+ eiedg |= BIT(extint);
+ }
+
+ if (type == IRQ_TYPE_LEVEL_HIGH ||
+ (!lvl && (type & IRQ_TYPE_LEVEL_HIGH))) {
+ eilvl |= BIT(extint);
+ eiedg &= ~BIT(extint);
+ }
+
+ if (type == IRQ_TYPE_EDGE_RISING ||
+ (!lvl && (type & IRQ_TYPE_EDGE_RISING))) {
+ eilvl |= BIT(extint);
+ eiedg |= BIT(extint);
+ }
+
+ /* Mask the interrupt */
+ val = readl_relaxed(pctl->exiu + EIMASK);
+ masked = val & BIT(extint); /* save status */
+ val |= BIT(extint);
+ writel_relaxed(val, pctl->exiu + EIMASK);
+
+ /* Program trigger */
+ writel_relaxed(eilvl, pctl->exiu + EILVL);
+ writel_relaxed(eiedg, pctl->exiu + EIEDG);
+
+ if (masked)
+ return;
+
+ /* UnMask the interrupt */
+ val = readl_relaxed(pctl->exiu + EIMASK);
+ val &= ~BIT(extint);
+ writel_relaxed(val, pctl->exiu + EIMASK);
+}
+
+static irqreturn_t m10v_gpio_irq_handler(int irq, void *data)
+{
+ struct m10v_pinctrl *pctl = data;
+ int i, pin;
+ u32 val;
+
+ for (i = 0; i < pctl->extints; i++)
+ if (pctl->fpint[i].irq == irq)
+ break;
+ if (i == pctl->extints) {
+ pr_err("%s:%d IRQ(%d)!\n", __func__, __LINE__, irq);
+ return IRQ_NONE;
+ }
+
+ if (!pctl->exiu)
+ return IRQ_NONE;
+
+ val = readl_relaxed(pctl->exiu + EIREQSTA);
+ if (!(val & BIT(i))) {
+ pr_err("%s:%d i=%d EIREQSTA=0x%x IRQ(%d)!\n",
+ __func__, __LINE__, i, val, irq);
+ return IRQ_NONE;
+ }
+
+ pin = pctl->fpint[i].pin;
+ generic_handle_irq(irq_linear_revmap(pctl->irqdom, pin));
+
+ return IRQ_HANDLED;
+}
+
+static void m10v_gpio_irq_enable(struct irq_data *data)
+{
+ struct m10v_pinctrl *pctl = irq_data_get_irq_chip_data(data);
+ int extint = pin_to_extint(pctl, irqd_to_hwirq(data));
+ unsigned long flags;
+ u32 val;
+
+ if (extint < 0 || !pctl->exiu)
+ return;
+
+ _set_mux(pctl, irqd_to_hwirq(data), true);
+ _set_direction(pctl, irqd_to_hwirq(data), true);
+
+ spin_lock_irqsave(&pctl->irq_lock, flags);
+
+ /* Clear before enabling */
+ writel_relaxed(BIT(extint), pctl->exiu + EIREQCLR);
+
+ /* UnMask the interrupt */
+ val = readl_relaxed(pctl->exiu + EIMASK);
+ val &= ~BIT(extint);
+ writel_relaxed(val, pctl->exiu + EIMASK);
+
+ spin_unlock_irqrestore(&pctl->irq_lock, flags);
+}
+
+static void m10v_gpio_irq_disable(struct irq_data *data)
+{
+ struct m10v_pinctrl *pctl = irq_data_get_irq_chip_data(data);
+ int extint = pin_to_extint(pctl, irqd_to_hwirq(data));
+ unsigned long flags;
+ u32 val;
+
+ if (extint < 0 || !pctl->exiu)
+ return;
+
+ spin_lock_irqsave(&pctl->irq_lock, flags);
+
+ /* Mask the interrupt */
+ val = readl_relaxed(pctl->exiu + EIMASK);
+ val |= BIT(extint);
+ writel_relaxed(val, pctl->exiu + EIMASK);
+
+ spin_unlock_irqrestore(&pctl->irq_lock, flags);
+}
+
+static int m10v_gpio_irq_set_type(struct irq_data *data, unsigned int type)
+{
+ struct m10v_pinctrl *pctl = irq_data_get_irq_chip_data(data);
+ int extint = pin_to_extint(pctl, irqd_to_hwirq(data));
+ unsigned long flags;
+
+ if (extint < 0 || !pctl->exiu)
+ return -EINVAL;
+
+ spin_lock_irqsave(&pctl->irq_lock, flags);
+
+ pctl->fpint[extint].type = type;
+ update_trigger(pctl, extint);
+
+ spin_unlock_irqrestore(&pctl->irq_lock, flags);
+
+ return 0;
+}
+
+void m10v_gpio_irq_ack(struct irq_data *data)
+{
+ struct m10v_pinctrl *pctl = irq_data_get_irq_chip_data(data);
+ int extint = pin_to_extint(pctl, irqd_to_hwirq(data));
+
+ if (extint < 0 || !pctl->exiu)
+ return;
+
+ writel_relaxed(BIT(extint), pctl->exiu + EIREQCLR);
+}
+
+void m10v_gpio_irq_mask(struct irq_data *data)
+{
+ struct m10v_pinctrl *pctl = irq_data_get_irq_chip_data(data);
+ int extint = pin_to_extint(pctl, irqd_to_hwirq(data));
+ unsigned long flags;
+ u32 val;
+
+ if (extint < 0 || !pctl->exiu)
+ return;
+
+ spin_lock_irqsave(&pctl->irq_lock, flags);
+
+ val = readl_relaxed(pctl->exiu + EIMASK);
+ val |= BIT(extint);
+ writel_relaxed(val, pctl->exiu + EIMASK);
+
+ spin_unlock_irqrestore(&pctl->irq_lock, flags);
+}
+
+void m10v_gpio_irq_unmask(struct irq_data *data)
+{
+ struct m10v_pinctrl *pctl = irq_data_get_irq_chip_data(data);
+ int extint = pin_to_extint(pctl, irqd_to_hwirq(data));
+ unsigned long flags;
+ u32 val;
+
+ if (extint < 0 || !pctl->exiu)
+ return;
+
+ spin_lock_irqsave(&pctl->irq_lock, flags);
+
+ update_trigger(pctl, extint);
+
+ val = readl_relaxed(pctl->exiu + EIMASK);
+ val &= ~BIT(extint);
+ writel_relaxed(val, pctl->exiu + EIMASK);
+
+ spin_unlock_irqrestore(&pctl->irq_lock, flags);
+}
+
+static struct irq_chip m10v_gpio_irq_chip = {
+ .name = "m10v-pin-irq",
+ .irq_enable = m10v_gpio_irq_enable,
+ .irq_disable = m10v_gpio_irq_disable,
+ .irq_set_type = m10v_gpio_irq_set_type,
+ .irq_mask = m10v_gpio_irq_mask,
+ .irq_unmask = m10v_gpio_irq_unmask,
+ .irq_ack = m10v_gpio_irq_ack,
+};
+
+static const struct of_device_id m10v_pmatch[] = {
+ { .compatible = "socionext,milbeaut-m10v-pinctrl" },
+ {},
+};
+
+static int m10v_pinctrl_probe(struct platform_device *pdev)
+{
+ struct device_node *np = pdev->dev.of_node;
+ struct pinctrl_dev *pctl_dev;
+ struct pin_irq_map fpint[32];
+ struct m10v_pinctrl *pctl;
+ struct pinctrl_desc *pd;
+ struct gpio_chip *gc;
+ struct resource *res;
+ int idx, i, ret, extints, tpins;
+
+ extints = of_irq_count(np);
+
+ pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl) +
+ sizeof(struct pin_irq_map) * extints,
+ GFP_KERNEL);
+ if (!pctl)
+ return -ENOMEM;
+
+ gpio_set = m10v_gpio_set;
+ bank_name = m10v_bank_name;
+ milbeaut_functions = m10v_functions;
+ tpins = M10V_TOTAL_PINS;
+
+ pd = &pctl->pd;
+ gc = &pctl->gc;
+ spin_lock_init(&pctl->lock);
+ spin_lock_init(&pctl->irq_lock);
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pinctrl");
+ pctl->base = devm_ioremap_resource(&pdev->dev, res);
+ if (!pctl->base)
+ return -EINVAL;
+
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "exiu");
+ if (res)
+ pctl->exiu = devm_ioremap_resource(&pdev->dev, res);
+ if (res && !IS_ERR(pctl->exiu)) {
+ writel_relaxed(~0, pctl->exiu + EIMASK); /* mask all */
+ writel_relaxed(~0, pctl->exiu + EIREQCLR); /* eoi all */
+ writel_relaxed(0, pctl->exiu + EISRCSEL); /* all fpint */
+ writel_relaxed(~0, pctl->exiu + EILVL); /* rising edge type*/
+ writel_relaxed(~0, pctl->exiu + EIEDG);
+ } else {
+ dev_info(&pdev->dev, "continuing without EXIU support\n");
+ pctl->exiu = NULL;
+ }
+
+ for (i = 0; i < tpins; i++) {
+ pctl->pins[i].number = i;
+ pctl->pins[i].name = &pctl->pin_names[4 * i];
+ snprintf(&pctl->pin_names[4 * i], 4, "P%c%d",
+ bank_name[i / PINS_PER_BANK], i % PINS_PER_BANK);
+ gpio_m10v_grps[i] = &pctl->pin_names[4 * i];
+ pctl->gpins[i][0] = i;
+ }
+ /* absent or incomplete entries allow all access */
+ pd->name = dev_name(&pdev->dev);
+ pd->pins = pctl->pins;
+ pd->npins = tpins;
+ pd->pctlops = &m10v_pctrl_ops;
+ pd->pmxops = &m10v_pmx_ops;
+ pd->confops = &m10v_pconf_ops;
+ pd->owner = THIS_MODULE;
+ pctl_dev = pinctrl_register(pd, &pdev->dev, pctl);
+ if (!pctl_dev) {
+ dev_err(&pdev->dev, "couldn't register pinctrl driver\n");
+ return -EINVAL;
+ }
+
+ pctl->extints = extints;
+
+ pctl->irqdom = irq_domain_add_linear(np, tpins,
+ &irq_domain_simple_ops, pctl);
+ idx = 0;
+ for (i = 0; i < tpins && idx < pctl->extints; i++) {
+ int irq;
+
+ snprintf(fpint[idx].irqname, 8, "pin-%d", i);
+ irq = platform_get_irq_byname(pdev, fpint[idx].irqname);
+ if (irq < 0)
+ continue;
+ fpint[idx].irq = irq;
+ fpint[idx].pin = i;
+ idx++;
+ }
+
+ for (idx = 0, i = 0; i < pctl->extints; i++) {
+ int j = 0, irq = platform_get_irq(pdev, i);
+
+ while (fpint[j].irq != irq)
+ j++;
+
+ snprintf(pctl->fpint[idx].irqname, 8, "pin-%d", fpint[j].pin);
+ pctl->fpint[idx].irq = fpint[j].irq;
+ pctl->fpint[idx].pin = fpint[j].pin;
+ idx++;
+ }
+
+ for (i = 0; i < pctl->extints; i++) {
+ int irq, err = devm_request_irq(&pdev->dev, pctl->fpint[i].irq,
+ m10v_gpio_irq_handler, IRQF_SHARED,
+ pctl->fpint[i].irqname, pctl);
+ if (err)
+ continue;
+
+ irq = irq_create_mapping(pctl->irqdom, pctl->fpint[i].pin);
+ irq_set_lockdep_class(irq, &gpio_lock_class,
+ &gpio_request_class);
+ irq_set_chip_and_handler(irq, &m10v_gpio_irq_chip,
+ handle_level_irq);
+ irq_set_chip_data(irq, pctl);
+ }
+
+ gc->base = -1;
+ gc->ngpio = tpins;
+ gc->label = dev_name(&pdev->dev);
+ gc->owner = THIS_MODULE;
+ gc->of_node = np;
+ gc->direction_input = m10v_gpio_direction_input;
+ gc->direction_output = m10v_gpio_direction_output;
+ gc->get = m10v_gpio_get;
+ gc->set = gpio_set;
+ gc->to_irq = m10v_gpio_to_irq;
+ gc->request = gpiochip_generic_request;
+ gc->free = gpiochip_generic_free;
+ ret = gpiochip_add(gc);
+ if (ret) {
+ dev_err(&pdev->dev, "Failed register gpiochip\n");
+ return ret;
+ }
+
+ ret = gpiochip_add_pin_range(gc, dev_name(&pdev->dev),
+ 0, 0, tpins);
+ if (ret) {
+ dev_err(&pdev->dev, "Failed to add pin range\n");
+ gpiochip_remove(gc);
+ return ret;
+ }
+
+ return 0;
+}
+
+static struct platform_driver m10v_pinctrl_driver = {
+ .probe = m10v_pinctrl_probe,
+ .driver = {
+ .name = "m10v-pinctrl",
+ .of_match_table = m10v_pmatch,
+ },
+};
+
+static int __init m10v_pinctrl_init(void)
+{
+ return platform_driver_register(&m10v_pinctrl_driver);
+}
+arch_initcall(m10v_pinctrl_init);
+
--
1.9.1
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH 12/14] ARM: dts: milbeaut: Add device tree set for the Milbeaut M10V board
2018-11-19 1:02 [PATCH 10/14] dt-bindings: pinctrl: milbeaut: Add Milbeaut M10V pinctrl description Sugaya Taichi
2018-11-19 1:02 ` [PATCH 11/14] pinctrl: milbeaut: Add Milbeaut M10V pinctrl Sugaya Taichi
@ 2018-11-19 1:02 ` Sugaya Taichi
2018-11-19 15:46 ` Rob Herring
2018-11-19 1:02 ` [PATCH 13/14] ARM: configs: Add Milbeaut M10V defconfig Sugaya Taichi
` (2 subsequent siblings)
4 siblings, 1 reply; 11+ messages in thread
From: Sugaya Taichi @ 2018-11-19 1:02 UTC (permalink / raw)
To: linux-clk, devicetree, linux-arm-kernel, linux-kernel, linux-serial
Cc: Michael Turquette, Stephen Boyd, Rob Herring, Mark Rutland,
Greg Kroah-Hartman, Daniel Lezcano, Thomas Gleixner,
Russell King, Jiri Slaby, Masami Hiramatsu, Jassi Brar,
Sugaya Taichi
Add devicetree for Milbeaut M10V SoC and M10V Evaluation board.
Signed-off-by: Sugaya Taichi <sugaya.taichi@socionext.com>
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/milbeaut-m10v-evb.dts | 35 +++
arch/arm/boot/dts/milbeaut-m10v-evb.dtsi | 17 ++
arch/arm/boot/dts/milbeaut-m10v.dtsi | 510 +++++++++++++++++++++++++++++++
4 files changed, 563 insertions(+)
create mode 100644 arch/arm/boot/dts/milbeaut-m10v-evb.dts
create mode 100644 arch/arm/boot/dts/milbeaut-m10v-evb.dtsi
create mode 100644 arch/arm/boot/dts/milbeaut-m10v.dtsi
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index b0e966d..ee6220b 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -1207,6 +1207,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
mt7623n-bananapi-bpi-r2.dtb \
mt8127-moose.dtb \
mt8135-evbp1.dtb
+dtb-$(CONFIG_MACH_M10V_EVB) += milbeaut-m10v-evb.dtb
dtb-$(CONFIG_ARCH_ZX) += zx296702-ad1.dtb
dtb-$(CONFIG_ARCH_ASPEED) += \
aspeed-ast2500-evb.dtb \
diff --git a/arch/arm/boot/dts/milbeaut-m10v-evb.dts b/arch/arm/boot/dts/milbeaut-m10v-evb.dts
new file mode 100644
index 0000000..af8d6e4
--- /dev/null
+++ b/arch/arm/boot/dts/milbeaut-m10v-evb.dts
@@ -0,0 +1,35 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Socionext Milbeaut M10V Evaluation Board */
+/dts-v1/;
+#include "milbeaut-m10v-evb.dtsi"
+
+/ {
+ cpus {
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0xf00>;
+ };
+ cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0xf01>;
+ };
+
+ cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0xf02>;
+ };
+ cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0xf03>;
+ };
+
+ };
+ trampoline: trampoline@0x0000F100 {
+ compatible = "socionext,smp-trampoline";
+ reg = <0x0000F100 0x100>;
+ };
+};
diff --git a/arch/arm/boot/dts/milbeaut-m10v-evb.dtsi b/arch/arm/boot/dts/milbeaut-m10v-evb.dtsi
new file mode 100644
index 0000000..fc35c0b
--- /dev/null
+++ b/arch/arm/boot/dts/milbeaut-m10v-evb.dtsi
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0
+#include "milbeaut-m10v.dtsi"
+
+/ {
+ model = "Socionext M10V EVB";
+ compatible = "socionext,sc2000a", "socionext,milbeaut-m10v-evb";
+ interrupt-parent = <&gic>;
+ chosen {
+ bootargs = "consoleblank=0 loglevel=8 init=/sbin/finit root=/dev/mmcblk0p2 rootwait ro console=ttyUSI0,115200n8 console=/dev/tty1 ";
+ linux,initrd-start = <0x4A000000>;
+ linux,initrd-end = <0x4BF00000>;
+ };
+ memory {
+ device_type = "memory";
+ reg = <0x40000000 0x80000000>;
+ };
+};
diff --git a/arch/arm/boot/dts/milbeaut-m10v.dtsi b/arch/arm/boot/dts/milbeaut-m10v.dtsi
new file mode 100644
index 0000000..4745dc6
--- /dev/null
+++ b/arch/arm/boot/dts/milbeaut-m10v.dtsi
@@ -0,0 +1,510 @@
+// SPDX-License-Identifier: GPL-2.0
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+#include "skeleton.dtsi"
+
+/ {
+ compatible = "socionext,sc2000a";
+ interrupt-parent = <&gic>;
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+
+ gic: interrupt-controller@1d000000 {
+ compatible = "arm,cortex-a7-gic";
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ reg = <0x1d001000 0x1000>, /* Distributer base and size */
+ <0x1d002000 0x1000>; /* CPU I/f base and size */
+ };
+
+ m10v-clk-tree@ {
+ compatible = "socionext,milbeaut-m10v-clk-regs";
+ reg = <0x1d021000 0x4000>;
+
+ clocks {
+ #address-cells = <0>;
+ #size-cells = <0>;
+
+ uclk40xi: uclk40xi {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <40000000>;
+ };
+
+ aumclki: aumclki {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <20000000>;
+ };
+
+ rtc32k: rtc32k {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ };
+
+ pxrefclk: pxrefclk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <100000000>;
+ };
+
+ pcisuppclk: pcisuppclk {
+ compatible = "fixed-factor-clock";
+ #clock-cells = <0>;
+ clocks = <&uclk40xi>;
+ clock-div = <20>;
+ clock-mult = <1>;
+ };
+
+ usb2_clk: usb2_clk {
+ compatible = "fixed-factor-clock";
+ #clock-cells = <0>;
+ clocks = <&uclk40xi>;
+ clock-div = <2>;
+ clock-mult = <1>;
+ };
+
+ pll1: pll1 {
+ compatible =
+ "socionext,milbeaut-m10v-pll-fixed-factor";
+ #clock-cells = <0>;
+ clocks = <&uclk40xi>;
+ offset = <1>;
+ clock-div = <1>;
+ clock-mult = <40>;
+ };
+
+ pll2: pll2 {
+ compatible =
+ "socionext,milbeaut-m10v-pll-fixed-factor";
+ #clock-cells = <0>;
+ clocks = <&uclk40xi>;
+ offset = <2>;
+ clock-div = <1>;
+ clock-mult = <30>;
+ };
+
+ pll6: pll6 { /* CLK 6-1 */
+ compatible =
+ "socionext,milbeaut-m10v-pll-fixed-factor";
+ #clock-cells = <0>;
+ clocks = <&uclk40xi>;
+ offset = <7>;
+ clock-div = <1>;
+ clock-mult = <35>;
+ };
+
+ pll7: pll7 { /* CLK 7-1 */
+ compatible =
+ "socionext,milbeaut-m10v-pll-fixed-factor";
+ #clock-cells = <0>;
+ clocks = <&uclk40xi>;
+ offset = <8>;
+ clock-div = <1>;
+ clock-mult = <40>;
+ };
+
+ pll9: pll9 { /* CA7CLK, ATCLK */
+ compatible = "fixed-factor-clock";
+ #clock-cells = <0>;
+ clocks = <&uclk40xi>;
+ clock-div = <1>;
+ clock-mult = <33>;
+ };
+
+ pll10: pll10 {
+ compatible =
+ "socionext,milbeaut-m10v-pll-fixed-factor";
+ #clock-cells = <0>;
+ clocks = <&uclk40xi>;
+ offset = <10>;
+ clock-div = <5>;
+ clock-mult = <108>;
+ };
+
+ pll11: pll11 { /* CLK 11-1 */
+ compatible =
+ "socionext,milbeaut-m10v-pll-fixed-factor";
+ #clock-cells = <0>;
+ clocks = <&uclk40xi>;
+ offset = <12>;
+ clock-div = <2>;
+ clock-mult = <75>;
+ };
+
+ emmcclk: emmcclk {
+ compatible = "socionext,milbeaut-m10v-clk-div";
+ #clock-cells = <0>;
+ clocks = <&pll11>;
+ offset = <28>; /* EMMCCLK */
+ mask = <0x3>;
+ ratios = <15 0x7 10 0x6 9 0x5 8 0x4>;
+ };
+
+ pll1_div_1_2: pll1_div_1_2 { /* CLK 1-2 */
+ compatible = "fixed-factor-clock";
+ #clock-cells = <0>;
+ clocks = <&pll1>;
+ clock-div = <2>;
+ clock-mult = <1>;
+ };
+
+ pll2_div_1_2: pll2_div_1_2 { /* CLK 2-2 */
+ compatible = "fixed-factor-clock";
+ #clock-cells = <0>;
+ clocks = <&pll2>;
+ clock-div = <2>;
+ clock-mult = <1>;
+ };
+
+ pll6_div_1_2: pll6_div_1_2 { /* CLK 6-2 */
+ compatible = "fixed-factor-clock";
+ #clock-cells = <0>;
+ clocks = <&pll6>;
+ clock-div = <2>;
+ clock-mult = <1>;
+ };
+
+ pll6_div_1_3: pll6_div_1_3 { /* CLK 6-3 */
+ compatible = "fixed-factor-clock";
+ #clock-cells = <0>;
+ clocks = <&pll6>;
+ clock-div = <3>;
+ clock-mult = <1>;
+ };
+
+ pll7_div_1_2: pll7_div_1_2 { /* CLK 7-2 */
+ compatible = "fixed-factor-clock";
+ #clock-cells = <0>;
+ clocks = <&pll7>;
+ clock-div = <2>;
+ clock-mult = <1>;
+ };
+
+ pll7_div_1_5: pll7_div_1_5 { /* CLK 7-5 */
+ compatible = "fixed-factor-clock";
+ #clock-cells = <0>;
+ clocks = <&pll7>;
+ clock-div = <5>;
+ clock-mult = <1>;
+ };
+
+ pll10_div_1_2: pll10_div_1_2 { /* CLK 10-2 */
+ compatible = "fixed-factor-clock";
+ #clock-cells = <0>;
+ clocks = <&pll10>;
+ clock-div = <2>;
+ clock-mult = <1>;
+ };
+
+ spiclk_mux_0: spiclk_mux_0 {
+ compatible = "socionext,milbeaut-m10v-clk-div";
+ #clock-cells = <0>;
+ clocks = <&pll10_div_1_2>;
+ offset = <227>; /* SPICLK */
+ mask = <0x3>;
+ ratios = <4 0x5 2 0x4>;
+ };
+
+ spiclk_mux_1: spiclk_mux_1 {
+ compatible = "socionext,milbeaut-m10v-clk-div";
+ #clock-cells = <0>;
+ clocks = <&pll7_div_1_2>;
+ offset = <227>; /* SPICLK */
+ mask = <0x3>;
+ ratios = <8 0x6>;
+ };
+
+ spiclk: spiclk {
+ compatible = "socionext,milbeaut-m10v-clk-mux";
+ #clock-cells = <0>;
+ clocks = <&spiclk_mux_0>, <&spiclk_mux_1>;
+ };
+
+ ca7wdclk: ca7wdclk {
+ compatible = "fixed-factor-clock";
+ #clock-cells = <0>;
+ clocks = <&pll2_div_1_2>;
+ clock-div = <12>;
+ clock-mult = <1>;
+ };
+
+ pll9_div_1_2: pll9_div_1_2 {
+ compatible = "fixed-factor-clock";
+ #clock-cells = <0>;
+ clocks = <&pll9>;
+ clock-div = <2>;
+ clock-mult = <1>;
+ };
+
+ mclk400: mclk400 {
+ compatible = "socionext,milbeaut-m10v-clk-div";
+ #clock-cells = <0>;
+ clocks = <&pll1_div_1_2>;
+ offset = <295>; /* MCLK400 */
+ mask = <0x3>;
+ ratios = <4 0x7 2 0x5>;
+ };
+
+ mclk200: mclk200 {
+ compatible = "socionext,milbeaut-m10v-clk-div";
+ #clock-cells = <0>;
+ clocks = <&pll1_div_1_2>;
+ offset = <291>; /* MCLK200 */
+ mask = <0x7>;
+ ratios = <8 0xf 4 0xb>;
+ };
+
+ aclk400: aclk400 {
+ compatible = "socionext,milbeaut-m10v-clk-div";
+ #clock-cells = <0>;
+ clocks = <&pll1_div_1_2>;
+ offset = <288>; /* ACLK400 */
+ mask = <0x3>;
+ ratios = <4 0x7 2 0x5>;
+ };
+
+ aclk300: aclk300 {
+ compatible = "socionext,milbeaut-m10v-clk-div";
+ #clock-cells = <0>;
+ clocks = <&pll2_div_1_2>;
+ offset = <352>; /* ACLK300 */
+ mask = <0x1>;
+ ratios = <6 0x3 4 0x2>;
+ };
+
+ aclk: aclk {
+ compatible = "socionext,milbeaut-m10v-clk-div";
+ #clock-cells = <0>;
+ clocks = <&pll1_div_1_2>;
+ offset = <276>; /* ACLK */
+ mask = <0x7>;
+ ratios = <8 0xf 4 0xb>;
+ };
+
+ aclkexs: aclkexs {
+ compatible = "socionext,milbeaut-m10v-clk-div";
+ #clock-cells = <0>;
+ clocks = <&pll1_div_1_2>;
+ offset = <272>; /* ACLKEXS */
+ mask = <0x7>;
+ ratios = <8 0xf 6 0xd 5 0xc 4 0xb>;
+ };
+
+ hclk: hclk {
+ compatible = "socionext,milbeaut-m10v-clk-div";
+ #clock-cells = <0>;
+ clocks = <&pll1_div_1_2>;
+ offset = <263>; /* HCLK */
+ mask = <0xf>;
+ ratios = <16 0x1f 8 0x17>;
+ };
+
+ hclkbmh: hclkbmh {
+ compatible = "socionext,milbeaut-m10v-clk-div";
+ #clock-cells = <0>;
+ clocks = <&pll1_div_1_2>;
+ offset = <268>; /* HCLKBMH */
+ mask = <0x7>;
+ ratios = <8 0xf 4 0xb>;
+ };
+
+ pclk: pclk {
+ compatible = "socionext,milbeaut-m10v-clk-div";
+ #clock-cells = <0>;
+ clocks = <&pll1_div_1_2>;
+ offset = <256>; /* PCLK */
+ mask = <0x3f>;
+ ratios = <32 0x5f 16 0x4f>;
+ };
+
+ pclkca7wd: pclkca7wd {
+ compatible = "fixed-factor-clock";
+ #clock-cells = <0>;
+ clocks = <&pll1_div_1_2>;
+ clock-div = <16>;
+ clock-mult = <1>;
+ };
+
+ rclk: rclk {
+ compatible = "socionext,milbeaut-m10v-clk-div";
+ #clock-cells = <0>;
+ clocks = <&pll10_div_1_2>;
+ offset = <0>; /* RCLK */
+ mask = <0x3>;
+ ratios = <64 0x7 48 0x6 32 0x5 16 0x4>;
+ };
+
+ uhs1clk0: uhs1clk0 {
+ compatible = "socionext,milbeaut-m10v-clk-div";
+ #clock-cells = <0>;
+ clocks = <&pll7>;
+ offset = <3>; /* UHS1CLK0 */
+ mask = <0xf>;
+ ratios = <16 0x14 8 0x13 4 0x12 3 0x11 2 0x10>;
+ };
+
+ uhs1clk1_div1: uhs1clk1_div1 {
+ compatible = "socionext,milbeaut-m10v-clk-div";
+ #clock-cells = <0>;
+ clocks = <&pll7>;
+ offset = <8>; /* UHS1CLK1 */
+ mask = <0xf>;
+ ratios = <16 0x14 8 0x13>;
+ };
+
+ uhs1clk1_div2: uhs1clk1_div2 {
+ compatible = "socionext,milbeaut-m10v-clk-div";
+ #clock-cells = <0>;
+ clocks = <&pll6_div_1_2>;
+ offset = <8>; /* UHS1CLK1 */
+ mask = <0xf>;
+ ratios = <1 0x18>;
+ };
+
+ uhs1clk1: uhs1clk1 {
+ compatible = "socionext,milbeaut-m10v-clk-mux";
+ #clock-cells = <0>;
+ clocks = <&uhs1clk1_div1>, <&uhs1clk1_div2>;
+ };
+
+ uhs1clk2_div1: uhs1clk2_div1 {
+ compatible = "socionext,milbeaut-m10v-clk-div";
+ #clock-cells = <0>;
+ clocks = <&pll7>;
+ offset = <13>; /* UHS1CLK2 */
+ mask = <0xf>;
+ ratios = <16 0x14 8 0x13 4 0x12>;
+ };
+
+ uhs1clk2_div2: uhs1clk2_div2 {
+ compatible = "socionext,milbeaut-m10v-clk-div";
+ #clock-cells = <0>;
+ clocks = <&pll6_div_1_2>;
+ offset = <13>; /* UHS1CLK2 */
+ mask = <0xf>;
+ ratios = <1 0x18>;
+ };
+
+ uhs1clk2: uhs1clk2 {
+ compatible = "socionext,milbeaut-m10v-clk-mux";
+ #clock-cells = <0>;
+ clocks = <&uhs1clk2_div1>, <&uhs1clk2_div2>;
+ };
+
+ uhs2clk: uhs2clk {
+ compatible = "socionext,milbeaut-m10v-clk-div";
+ #clock-cells = <0>;
+ clocks = <&pll6_div_1_3>;
+ offset = <18>; /* UHS2CLK */
+ mask = <0x7>;
+ ratios = <18 0xf 16 0xe 14 0xd 13 0xc
+ 12 0xb 11 0xa 10 0x9 9 0x8>;
+ };
+
+ nfclk_div1: nfclk_div1 {
+ compatible = "socionext,milbeaut-m10v-clk-div";
+ #clock-cells = <0>;
+ clocks = <&pll7_div_1_2>;
+ offset = <22>; /* NFCLK */
+ mask = <0x1f>;
+ ratios = <40 0x24 16 0x23 13 0x22 10 0x21
+ 8 0x20>;
+ };
+
+ nfclk_div2: nfclk_div2 {
+ compatible = "socionext,milbeaut-m10v-clk-div";
+ #clock-cells = <0>;
+ clocks = <&pll7_div_1_5>;
+ offset = <22>; /* NFCLK */
+ mask = <0x1f>;
+ ratios = <10 0x28>;
+ };
+
+ nfclk: nfclk {
+ compatible = "socionext,milbeaut-m10v-clk-mux";
+ #clock-cells = <0>;
+ clocks = <&nfclk_div1>, <&nfclk_div2>;
+ };
+
+ clk5: clk5 {
+ compatible = "socionext,milbeaut-m10v-clk-div";
+ #clock-cells = <0>;
+ clocks = <&pll10_div_1_2>;
+ offset = <239>; /* NETAUSEL */
+ mask = <0x3>;
+ ratios = <64 0x7 48 0x6 32 0x5 16 0x4>;
+ };
+ };
+ };
+
+ peri-timer@1e000000 { /* 32-bit Reload Timers */
+ compatible = "socionext,milbeaut-m10v-timer";
+ reg = <0x1e000050 0x10>, <0x1e000060 0x10>;
+ interrupts = <0 91 4>;
+ clocks = <&rclk>;
+ };
+
+ timer { /* The Generic Timer */
+ compatible = "arm,armv7-timer";
+ interrupts = <GIC_PPI 13
+ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
+ <GIC_PPI 14
+ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
+ <GIC_PPI 11
+ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
+ <GIC_PPI 10
+ (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+ clock-frequency = <40000000>;//40M
+ always-on;
+ arm,cpu-registers-not-fw-configured;
+ };
+
+ dummy_clk: dummy_clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <50000000>;
+ };
+
+ pinctrl: pinctrl@1d022000 {
+ compatible = "socionext,milbeaut-m10v-pinctrl";
+ reg = <0x1d022000 0x1000>,
+ <0x1c26f000 0x1000>;
+ reg-names = "pinctrl", "exiu";
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ clocks = <&dummy_clk>;
+ interrupts = <0 54 4>, <0 55 4>, <0 56 4>, <0 57 4>,
+ <0 58 4>, <0 59 4>, <0 60 4>, <0 61 4>,
+ <0 62 4>, <0 63 4>, <0 64 4>, <0 65 4>,
+ <0 66 4>, <0 67 4>, <0 68 4>, <0 69 4>;
+ interrupt-names = "pin-48", "pin-49", "pin-50", "pin-51",
+ "pin-52", "pin-53", "pin-54", "pin-55",
+ "pin-56", "pin-57", "pin-58", "pin-59",
+ "pin-60", "pin-61", "pin-62", "pin-63";
+
+ usio1_pins: usio1_pins {
+ pins = "PE4", "PE5", "P87";
+ function = "usio1";
+ };
+ };
+
+ usio1: usio_uart@1e700010 { /* PE4, PE5 */
+ /* Enable this as ttyUSI0 */
+ index = <0>;
+ compatible = "socionext,milbeaut-m10v-usio-uart";
+ reg = <0x1e700010 0x10>;
+ interrupts = <0 141 0x4>, <0 149 0x4>;
+ interrupt-names = "rx", "tx";
+ clocks = <&hclk>;
+ };
+};
--
1.9.1
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH 13/14] ARM: configs: Add Milbeaut M10V defconfig
2018-11-19 1:02 [PATCH 10/14] dt-bindings: pinctrl: milbeaut: Add Milbeaut M10V pinctrl description Sugaya Taichi
2018-11-19 1:02 ` [PATCH 11/14] pinctrl: milbeaut: Add Milbeaut M10V pinctrl Sugaya Taichi
2018-11-19 1:02 ` [PATCH 12/14] ARM: dts: milbeaut: Add device tree set for the Milbeaut M10V board Sugaya Taichi
@ 2018-11-19 1:02 ` Sugaya Taichi
2018-11-19 1:02 ` [PATCH 14/14] MAINTAINERS: Add entry to MAINTAINERS for Milbeaut Sugaya Taichi
2018-12-04 23:11 ` [PATCH 10/14] dt-bindings: pinctrl: milbeaut: Add Milbeaut M10V pinctrl description Rob Herring
4 siblings, 0 replies; 11+ messages in thread
From: Sugaya Taichi @ 2018-11-19 1:02 UTC (permalink / raw)
To: linux-clk, devicetree, linux-arm-kernel, linux-kernel, linux-serial
Cc: Michael Turquette, Stephen Boyd, Rob Herring, Mark Rutland,
Greg Kroah-Hartman, Daniel Lezcano, Thomas Gleixner,
Russell King, Jiri Slaby, Masami Hiramatsu, Jassi Brar,
Sugaya Taichi
This patch adds the minimal defconfig for the Milbeaut M10V.
Signed-off-by: Sugaya Taichi <sugaya.taichi@socionext.com>
---
arch/arm/configs/milbeaut_m10v_defconfig | 364 +++++++++++++++++++++++++++++++
1 file changed, 364 insertions(+)
create mode 100644 arch/arm/configs/milbeaut_m10v_defconfig
diff --git a/arch/arm/configs/milbeaut_m10v_defconfig b/arch/arm/configs/milbeaut_m10v_defconfig
new file mode 100644
index 0000000..90c22f8
--- /dev/null
+++ b/arch/arm/configs/milbeaut_m10v_defconfig
@@ -0,0 +1,364 @@
+# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_DEFAULT_HOSTNAME="mlbel"
+CONFIG_SYSVIPC=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_FHANDLE=y
+CONFIG_NO_HZ_FULL=y
+CONFIG_NO_HZ_FULL_ALL=y
+CONFIG_NO_HZ_FULL_SYSIDLE=y
+CONFIG_NO_HZ_FULL_SYSIDLE_SMALL=4
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_BSD_PROCESS_ACCT_V3=y
+CONFIG_TASKSTATS=y
+CONFIG_TASK_DELAY_ACCT=y
+CONFIG_TASK_XACCT=y
+CONFIG_TASK_IO_ACCOUNTING=y
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_CGROUPS=y
+CONFIG_CGROUP_DEBUG=y
+CONFIG_CPUSETS=y
+CONFIG_CGROUP_SCHED=y
+CONFIG_CFS_BANDWIDTH=y
+CONFIG_RT_GROUP_SCHED=y
+CONFIG_NAMESPACES=y
+CONFIG_USER_NS=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_KALLSYMS_ALL=y
+CONFIG_EMBEDDED=y
+# CONFIG_COMPAT_BRK is not set
+CONFIG_SLAB=y
+CONFIG_PROFILING=y
+CONFIG_OPROFILE=m
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_ARCH_MILBEAUT=y
+CONFIG_ARCH_MILBEAUT_M10V=y
+# CONFIG_CACHE_L2X0 is not set
+CONFIG_ARM_ERRATA_754322=y
+CONFIG_ARM_ERRATA_775420=y
+# CONFIG_PCI is not set
+# CONFIG_PCI_DEBUG is not set
+# CONFIG_PCI_HOST_GENERIC is not set
+# CONFIG_PCIE_SN_DW_PLAT is not set
+# CONFIG_PCI_MSI is not set
+# CONFIG_PCIEPORTBUS is not set
+# CONFIG_PCIEAER is not set
+# CONFIG_PCIEASPM is not set
+CONFIG_SMP=y
+# CONFIG_ARM_CPU_TOPOLOGY is not set
+CONFIG_HAVE_ARM_ARCH_TIMER=y
+CONFIG_VMSPLIT_2G=y
+CONFIG_PREEMPT=y
+CONFIG_THUMB2_KERNEL=y
+CONFIG_HIGHMEM=y
+# CONFIG_COMPACTION is not set
+CONFIG_CMA=y
+# CONFIG_ATAGS is not set
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_ARM_APPENDED_DTB=y
+CONFIG_KEXEC=y
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
+CONFIG_CPUFREQ_DT=y
+CONFIG_CPU_IDLE=y
+CONFIG_VFP=y
+CONFIG_NEON=y
+CONFIG_KERNEL_MODE_NEON=y
+CONFIG_PM_RUNTIME=y
+CONFIG_PM_DEBUG=y
+CONFIG_WQ_POWER_EFFICIENT_DEFAULT=y
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_PACKET_DIAG=m
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_MROUTE=y
+CONFIG_IP_PIMSM_V1=y
+CONFIG_IP_PIMSM_V2=y
+CONFIG_SYN_COOKIES=y
+CONFIG_NET_IPVTI=m
+CONFIG_INET_AH=y
+CONFIG_INET_ESP=y
+CONFIG_INET_IPCOMP=y
+CONFIG_INET_XFRM_MODE_TRANSPORT=m
+CONFIG_INET_XFRM_MODE_TUNNEL=m
+CONFIG_INET_XFRM_MODE_BEET=m
+CONFIG_INET_UDP_DIAG=m
+CONFIG_TCP_CONG_ADVANCED=y
+CONFIG_IP_SCTP=m
+CONFIG_SCTP_COOKIE_HMAC_SHA1=y
+CONFIG_TIPC=y
+CONFIG_L2TP=m
+CONFIG_L2TP_DEBUGFS=m
+CONFIG_L2TP_V3=y
+CONFIG_L2TP_IP=y
+CONFIG_L2TP_ETH=y
+CONFIG_IPX=m
+CONFIG_NETLINK_MMAP=y
+CONFIG_NETLINK_DIAG=y
+CONFIG_CFG80211=y
+CONFIG_NL80211_TESTMODE=y
+CONFIG_CFG80211_DEVELOPER_WARNINGS=y
+CONFIG_CFG80211_REG_DEBUG=y
+CONFIG_CFG80211_INTERNAL_REGDB=y
+CONFIG_CFG80211_WEXT=y
+CONFIG_MAC80211=y
+# CONFIG_MAC80211_RC_MINSTREL is not set
+CONFIG_MAC80211_LEDS=y
+CONFIG_RFKILL=y
+CONFIG_RFKILL_INPUT=y
+CONFIG_RFKILL_REGULATOR=y
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+CONFIG_DMA_CMA=y
+CONFIG_CMA_SIZE_MBYTES=16
+CONFIG_MTD=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_M25P80=y
+CONFIG_MTD_NAND=y
+CONFIG_MTD_NAND_CDN_HPNFC=y
+CONFIG_MTD_NAND_CDN_HPNFC_DT=y
+CONFIG_MTD_NAND_PLATFORM=y
+CONFIG_MTD_SPI_NOR=y
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_BEB_LIMIT=3
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_LOOP_MIN_COUNT=2
+CONFIG_BLK_DEV_RAM=y
+CONFIG_SCSI=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_NETDEVICES=y
+CONFIG_MACVLAN=y
+CONFIG_TUN=y
+CONFIG_VETH=y
+# CONFIG_NET_CADENCE is not set
+# CONFIG_NET_VENDOR_BROADCOM is not set
+# CONFIG_NET_VENDOR_CIRRUS is not set
+# CONFIG_NET_VENDOR_FARADAY is not set
+# CONFIG_NET_VENDOR_INTEL is not set
+# CONFIG_NET_VENDOR_MARVELL is not set
+# CONFIG_NET_VENDOR_MICREL is not set
+# CONFIG_NET_VENDOR_NATSEMI is not set
+CONFIG_R8169=y
+# CONFIG_NET_VENDOR_SEEQ is not set
+# CONFIG_NET_VENDOR_SMSC is not set
+# CONFIG_NET_SOCIONEXT_OGMA=y
+# CONFIG_NET_VENDOR_STMICRO is not set
+# CONFIG_NET_VENDOR_WIZNET is not set
+CONFIG_REALTEK_PHY=y
+CONFIG_MWIFIEX=m
+CONFIG_MWIFIEX_SDIO=m
+CONFIG_INPUT_POLLDEV=y
+# CONFIG_INPUT_MOUSEDEV is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+CONFIG_SERIO_LIBPS2=y
+CONFIG_LEGACY_PTY_COUNT=4
+# CONFIG_DEVKMEM is not set
+CONFIG_SERIAL_8250=y
+# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set
+CONFIG_SERIAL_8250_CONSOLE=y
+# CONFIG_SERIAL_8250_DMA is not set
+CONFIG_SERIAL_8250_EXTENDED=y
+CONFIG_SERIAL_8250_DW=y
+CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_SERIAL_M10V_USIO=y
+CONFIG_SERIAL_M10V_USIO_CONSOLE=y
+# CONFIG_HW_RANDOM is not set
+# CONFIG_I2C is not set
+# CONFIG_I2C_BOARDINFO is not set
+# CONFIG_I2C_COMPAT is not set
+# CONFIG_I2C_CHARDEV is not set
+# CONFIG_I2C_MUX is not set
+# CONFIG_I2C_HELPER_AUTO is not set
+# CONFIG_I2C_ALGOBIT is not set
+# CONFIG_I2C_SNI_M10V is not set
+CONFIG_SPI=y
+# CONFIG_SPI_SN_USIO=y
+#CONFIG_SPI_SNI is not set
+#CONFIG_SPI_SPIDEV is not set
+CONFIG_GPIOLIB=y
+CONFIG_GPIO_SYSFS=y
+CONFIG_GPIO_PCA953X=y
+CONFIG_GPIO_PCA953X_IRQ=y
+# CONFIG_HWMON is not set
+CONFIG_WATCHDOG=y
+CONFIG_SOFT_WATCHDOG=m
+CONFIG_REGULATOR=y
+CONFIG_REGULATOR_DEBUG=y
+CONFIG_REGULATOR_S6AP412=y
+CONFIG_MEDIA_SUPPORT=y
+CONFIG_MEDIA_CAMERA_SUPPORT=y
+CONFIG_MEDIA_CONTROLLER=y
+CONFIG_VIDEO_V4L2_SUBDEV_API=y
+CONFIG_VIDEO_ADV_DEBUG=y
+CONFIG_MEDIA_USB_SUPPORT=y
+CONFIG_USB_VIDEO_CLASS=y
+# CONFIG_USB_GSPCA is not set
+CONFIG_V4L_PLATFORM_DRIVERS=y
+CONFIG_SOC_CAMERA=y
+CONFIG_SOC_CAMERA_PLATFORM=y
+CONFIG_V4L_MEM2MEM_DRIVERS=y
+CONFIG_V4L_TEST_DRIVERS=y
+CONFIG_VIDEO_VIVID=m
+CONFIG_VIDEO_VIVID_MAX_DEVS=64
+CONFIG_FB=y
+# CONFIG_VGA_ARB is not set
+# CONFIG_USB is not set
+# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
+# CONFIG_USB_MON is not set
+# CONFIG_USB_XHCI_HCD is not set
+# CONFIG_USB_EHCI_HCD is not set
+# CONFIG_USB_EHCI_ROOT_HUB_TT is not set
+# CONFIG_USB_EHCI_HCD_PLATFORM is not set
+# CONFIG_USB_OHCI_HCD is not set
+# CONFIG_USB_OHCI_HCD_PCI is not set
+# CONFIG_USB_OHCI_HCD_PLATFORM is not set
+# CONFIG_USB_STORAGE is not set
+# CONFIG_USB_SERIAL is not set
+# CONFIG_USB_SERIAL_GENERIC is not set
+# CONFIG_USB_SERIAL_CP210X is not set
+# CONFIG_USB_SERIAL_FTDI_SIO is not set
+# CONFIG_USB_SERIAL_PL2303 is not set
+# CONFIG_USB_ULPI is not set
+# CONFIG_USB_GADGET is not set
+# CONFIG_USB_DWC3 is not set
+# CONFIG_USB_DWC3_PCI is not set
+# CONFIG_USB_DWC3_OTG is not set
+# CONFIG_USB_DWC3_SN is not set
+# CONFIG_USB_DWC3_OF_SIMPLE is not set
+# CONFIG_USB_GADGET_SN_LAP is not set
+# CONFIG_USB_CONFIGFS is not set
+# CONFIG_USB_CONFIGFS_ACM is not set
+# CONFIG_USB_CONFIGFS_MASS_STORAGE is not set
+# CONFIG_USB_CONFIGFS_F_MTP is not set
+# CONFIG_USB_CONFIGFS_F_UVC is not set
+# CONFIG_USB_CONFIGFS_UEVENT is not set
+# CONFIG_MMC is not set
+# CONFIG_MMC_SDHCI is not set
+# CONFIG_MMC_SDHCI_PLTFM is not set
+# CONFIG_MMC_SDHCI_F_SDH30 is not set
+# CONFIG_MMC_SDHCI_F_EMMC50 is not set
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+CONFIG_LEDS_GPIO=y
+CONFIG_LEDS_TRIGGER_TIMER=y
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+CONFIG_RTC_CLASS=y
+# CONFIG_RTC_HCTOSYS is not set
+# CONFIG_RTC_SYSTOHC is not set
+CONFIG_RTC_DEBUG=y
+CONFIG_RTC_DRV_RX8025=y
+CONFIG_DMADEVICES=y
+CONFIG_MB86S7X_HDMAC=y
+CONFIG_MB8AC0300_XDMAC=y
+CONFIG_UIO=y
+CONFIG_UIO_SNI=y
+# CONFIG_IOMMU_SUPPORT is not set
+CONFIG_PWM=y
+# CONFIG_PWM_SYSFS is not set
+CONFIG_PWM_M10V=y
+CONFIG_RESET_CONTROLLER=y
+CONFIG_EXFAT=y
+CONFIG_EXT4_FS=y
+# CONFIG_EXT4_USE_FOR_EXT23 is not set
+# CONFIG_XFS_FS is not set
+CONFIG_FANOTIFY=y
+CONFIG_FANOTIFY_ACCESS_PERMISSIONS=y
+CONFIG_QUOTA=y
+CONFIG_AUTOFS4_FS=y
+# CONFIG_FUSE_FS is not set
+CONFIG_FSCACHE=y
+CONFIG_FSCACHE_STATS=y
+CONFIG_FSCACHE_HISTOGRAM=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=932
+CONFIG_TMPFS=y
+CONFIG_TMPFS_POSIX_ACL=y
+CONFIG_UBIFS_FS=y
+CONFIG_UBIFS_FS_ADVANCED_COMPR=y
+CONFIG_ROMFS_FS=y
+CONFIG_ROMFS_BACKED_BY_BOTH=y
+CONFIG_NFS_FS=m
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_CODEPAGE_737=y
+CONFIG_NLS_CODEPAGE_775=y
+CONFIG_NLS_CODEPAGE_850=y
+CONFIG_NLS_CODEPAGE_852=y
+CONFIG_NLS_CODEPAGE_855=y
+CONFIG_NLS_CODEPAGE_857=y
+CONFIG_NLS_CODEPAGE_860=y
+CONFIG_NLS_CODEPAGE_861=y
+CONFIG_NLS_CODEPAGE_862=y
+CONFIG_NLS_CODEPAGE_863=y
+CONFIG_NLS_CODEPAGE_864=y
+CONFIG_NLS_CODEPAGE_865=y
+CONFIG_NLS_CODEPAGE_866=y
+CONFIG_NLS_CODEPAGE_869=y
+CONFIG_NLS_CODEPAGE_936=y
+CONFIG_NLS_CODEPAGE_950=y
+CONFIG_NLS_CODEPAGE_932=y
+CONFIG_NLS_CODEPAGE_949=y
+CONFIG_NLS_CODEPAGE_874=y
+CONFIG_NLS_ISO8859_8=y
+CONFIG_NLS_CODEPAGE_1250=y
+CONFIG_NLS_CODEPAGE_1251=y
+CONFIG_NLS_ASCII=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_NLS_ISO8859_2=y
+CONFIG_NLS_ISO8859_3=y
+CONFIG_NLS_ISO8859_4=y
+CONFIG_NLS_ISO8859_5=y
+CONFIG_NLS_ISO8859_6=y
+CONFIG_NLS_ISO8859_7=y
+CONFIG_NLS_ISO8859_9=y
+CONFIG_NLS_ISO8859_13=y
+CONFIG_NLS_ISO8859_14=y
+CONFIG_NLS_ISO8859_15=y
+CONFIG_NLS_KOI8_R=y
+CONFIG_NLS_KOI8_U=y
+CONFIG_NLS_MAC_ROMAN=y
+CONFIG_NLS_MAC_CELTIC=y
+CONFIG_NLS_MAC_CENTEURO=y
+CONFIG_NLS_MAC_CROATIAN=y
+CONFIG_NLS_MAC_CYRILLIC=y
+CONFIG_NLS_MAC_GAELIC=y
+CONFIG_NLS_MAC_GREEK=y
+CONFIG_NLS_MAC_ICELAND=y
+CONFIG_NLS_MAC_INUIT=y
+CONFIG_NLS_MAC_ROMANIAN=y
+CONFIG_NLS_MAC_TURKISH=y
+CONFIG_NLS_UTF8=y
+CONFIG_IPCU_FS=y
+# CONFIG_TEST_IPCU_FS is not set
+CONFIG_PRINTK_TIME=y
+CONFIG_DYNAMIC_DEBUG=y
+CONFIG_DEBUG_INFO=y
+#CONFIG_DEBUG_INFO_REDUCED is not set
+CONFIG_DEBUG_FS=y
+CONFIG_DEBUG_GIC_BL=y
+CONFIG_HEADERS_CHECK=y
+CONFIG_DEBUG_SECTION_MISMATCH=y
+CONFIG_DEBUG_MEMORY_INIT=y
+# CONFIG_DEBUG_PREEMPT is not set
+CONFIG_RCU_TORTURE_TEST=m
+CONFIG_RCU_CPU_STALL_TIMEOUT=60
+CONFIG_KGDB=y
+CONFIG_DEBUG_USER=y
+CONFIG_DEBUG_LL=y
+CONFIG_DEBUG_LL_MILBEAUT_UART=y
+CONFIG_EARLY_PRINTK=y
+# CONFIG_EARLY_PRINTK_DIRECT is not set
+CONFIG_KEYS=y
+CONFIG_ENCRYPTED_KEYS=y
+CONFIG_SECURITY=y
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+# CONFIG_CRYPTO_HW is not set
+CONFIG_FONTS=y
--
1.9.1
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH 14/14] MAINTAINERS: Add entry to MAINTAINERS for Milbeaut
2018-11-19 1:02 [PATCH 10/14] dt-bindings: pinctrl: milbeaut: Add Milbeaut M10V pinctrl description Sugaya Taichi
` (2 preceding siblings ...)
2018-11-19 1:02 ` [PATCH 13/14] ARM: configs: Add Milbeaut M10V defconfig Sugaya Taichi
@ 2018-11-19 1:02 ` Sugaya Taichi
2018-12-04 23:11 ` [PATCH 10/14] dt-bindings: pinctrl: milbeaut: Add Milbeaut M10V pinctrl description Rob Herring
4 siblings, 0 replies; 11+ messages in thread
From: Sugaya Taichi @ 2018-11-19 1:02 UTC (permalink / raw)
To: linux-clk, devicetree, linux-arm-kernel, linux-kernel, linux-serial
Cc: Michael Turquette, Stephen Boyd, Rob Herring, Mark Rutland,
Greg Kroah-Hartman, Daniel Lezcano, Thomas Gleixner,
Russell King, Jiri Slaby, Masami Hiramatsu, Jassi Brar,
Sugaya Taichi
Add entry to MAINTAINERS for Milbeaut that supported minimal drivers.
Signed-off-by: Sugaya Taichi <sugaya.taichi@socionext.com>
---
MAINTAINERS | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 0abecc5..31dd29f 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1782,6 +1782,15 @@ F: drivers/watchdog/sama5d4_wdt.c
X: drivers/input/touchscreen/atmel_mxt_ts.c
X: drivers/net/wireless/atmel/
+ARM/MILBEAUT ARCHITECTURE
+M: Taichi Sugaya <sugaya.taichi@socionext.com>
+M: Takao Orito <orito.takao@socionext.com>
+L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
+S: Maintained
+F: arch/arm/boot/dts/milbeaut*
+F: arch/arm/mach-milbeaut/
+N: milbeaut
+
ARM/MIOA701 MACHINE SUPPORT
M: Robert Jarzmik <robert.jarzmik@free.fr>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
--
1.9.1
^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [PATCH 12/14] ARM: dts: milbeaut: Add device tree set for the Milbeaut M10V board
2018-11-19 1:02 ` [PATCH 12/14] ARM: dts: milbeaut: Add device tree set for the Milbeaut M10V board Sugaya Taichi
@ 2018-11-19 15:46 ` Rob Herring
2018-11-21 2:36 ` sugaya.taichi
0 siblings, 1 reply; 11+ messages in thread
From: Rob Herring @ 2018-11-19 15:46 UTC (permalink / raw)
To: sugaya.taichi, ARM-SoC Maintainers
Cc: linux-clk, devicetree,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE,
linux-kernel, open list:SERIAL DRIVERS, Michael Turquette,
Stephen Boyd, Mark Rutland, Greg Kroah-Hartman, Daniel Lezcano,
Thomas Gleixner, Russell King, Jiri Slaby, Masami Hiramatsu,
Jassi Brar
On Sun, Nov 18, 2018 at 7:01 PM Sugaya Taichi
<sugaya.taichi@socionext.com> wrote:
>
> Add devicetree for Milbeaut M10V SoC and M10V Evaluation board.
>
> Signed-off-by: Sugaya Taichi <sugaya.taichi@socionext.com>
> ---
> arch/arm/boot/dts/Makefile | 1 +
> arch/arm/boot/dts/milbeaut-m10v-evb.dts | 35 +++
> arch/arm/boot/dts/milbeaut-m10v-evb.dtsi | 17 ++
> arch/arm/boot/dts/milbeaut-m10v.dtsi | 510 +++++++++++++++++++++++++++++++
I'm not seeing why you need this split into 3 files instead of 2.
> 4 files changed, 563 insertions(+)
> create mode 100644 arch/arm/boot/dts/milbeaut-m10v-evb.dts
> create mode 100644 arch/arm/boot/dts/milbeaut-m10v-evb.dtsi
> create mode 100644 arch/arm/boot/dts/milbeaut-m10v.dtsi
Build your dtb with 'W=12' and fix any warnings.
>
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index b0e966d..ee6220b 100644
> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -1207,6 +1207,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
> mt7623n-bananapi-bpi-r2.dtb \
> mt8127-moose.dtb \
> mt8135-evbp1.dtb
> +dtb-$(CONFIG_MACH_M10V_EVB) += milbeaut-m10v-evb.dtb
ARM SoC maintainers,
Can we start at least start putting new SoCs in vendor subdirs? This
one doesn't appear to share anything.
> dtb-$(CONFIG_ARCH_ZX) += zx296702-ad1.dtb
> dtb-$(CONFIG_ARCH_ASPEED) += \
> aspeed-ast2500-evb.dtb \
> diff --git a/arch/arm/boot/dts/milbeaut-m10v-evb.dts b/arch/arm/boot/dts/milbeaut-m10v-evb.dts
> new file mode 100644
> index 0000000..af8d6e4
> --- /dev/null
> +++ b/arch/arm/boot/dts/milbeaut-m10v-evb.dts
> @@ -0,0 +1,35 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/* Socionext Milbeaut M10V Evaluation Board */
> +/dts-v1/;
> +#include "milbeaut-m10v-evb.dtsi"
> +
> +/ {
> + cpus {
cpus is not board specific.
> + cpu@0 {
Unit-address is wrong. Should be '@f00' to match reg.
> + device_type = "cpu";
> + compatible = "arm,cortex-a7";
> + reg = <0xf00>;
> + };
> + cpu@1 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a7";
> + reg = <0xf01>;
> + };
> +
> + cpu@2 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a7";
> + reg = <0xf02>;
> + };
> + cpu@3 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a7";
> + reg = <0xf03>;
> + };
> +
> + };
> + trampoline: trampoline@0x0000F100 {
Also, not board specific.
This should be under a simple-bus node. The unit-address should be '@f100'.
> + compatible = "socionext,smp-trampoline";
> + reg = <0x0000F100 0x100>;
Use lowercase hex.
> + };
> +};
> diff --git a/arch/arm/boot/dts/milbeaut-m10v-evb.dtsi b/arch/arm/boot/dts/milbeaut-m10v-evb.dtsi
> new file mode 100644
> index 0000000..fc35c0b
> --- /dev/null
> +++ b/arch/arm/boot/dts/milbeaut-m10v-evb.dtsi
> @@ -0,0 +1,17 @@
> +// SPDX-License-Identifier: GPL-2.0
> +#include "milbeaut-m10v.dtsi"
> +
> +/ {
> + model = "Socionext M10V EVB";
> + compatible = "socionext,sc2000a", "socionext,milbeaut-m10v-evb";
Wrong order. And these need to be documented.
> + interrupt-parent = <&gic>;
> + chosen {
> + bootargs = "consoleblank=0 loglevel=8 init=/sbin/finit root=/dev/mmcblk0p2 rootwait ro console=ttyUSI0,115200n8 console=/dev/tty1 ";
Most of these options look user specific and should be dropped. Use
'stdout-path' to specify the default console.
> + linux,initrd-start = <0x4A000000>;
> + linux,initrd-end = <0x4BF00000>;
initrd should be filled in by the bootloader.
> + };
> + memory {
Needs a unit-address.
> + device_type = "memory";
> + reg = <0x40000000 0x80000000>;
> + };
> +};
> diff --git a/arch/arm/boot/dts/milbeaut-m10v.dtsi b/arch/arm/boot/dts/milbeaut-m10v.dtsi
> new file mode 100644
> index 0000000..4745dc6
> --- /dev/null
> +++ b/arch/arm/boot/dts/milbeaut-m10v.dtsi
> @@ -0,0 +1,510 @@
> +// SPDX-License-Identifier: GPL-2.0
> +#include <dt-bindings/interrupt-controller/irq.h>
> +#include <dt-bindings/input/input.h>
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> +#include "skeleton.dtsi"
Don't use skeleton.dtsi. It is deprecated.
> +
> +/ {
> + compatible = "socionext,sc2000a";
> + interrupt-parent = <&gic>;
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
Just move this to the other file with the cpu nodes.
> +
> +
> + gic: interrupt-controller@1d000000 {
> + compatible = "arm,cortex-a7-gic";
> + interrupt-controller;
> + #interrupt-cells = <3>;
> + reg = <0x1d001000 0x1000>, /* Distributer base and size */
> + <0x1d002000 0x1000>; /* CPU I/f base and size */
> + };
> +
> + m10v-clk-tree@ {
unit-address
> + compatible = "socionext,milbeaut-m10v-clk-regs";
> + reg = <0x1d021000 0x4000>;
> +
> + clocks {
> + #address-cells = <0>;
> + #size-cells = <0>;
> +
> + uclk40xi: uclk40xi {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <40000000>;
> + };
Any fixed clocks from oscillators on the board should be at the top
level and defined as inputs to the clock controller node with a
'clocks' property.
> +
> + aumclki: aumclki {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <20000000>;
> + };
> +
> + rtc32k: rtc32k {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <32768>;
> + };
> +
> + pxrefclk: pxrefclk {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <100000000>;
> + };
> +
> + pcisuppclk: pcisuppclk {
> + compatible = "fixed-factor-clock";
> + #clock-cells = <0>;
> + clocks = <&uclk40xi>;
> + clock-div = <20>;
> + clock-mult = <1>;
> + };
Please look at any recent example of clock bindings. We don't try to
describe every divider, mux, gate, etc. in DT, but just clock
controller blocks with all the output clocks enumerated in clock
cells.
> +
> + usb2_clk: usb2_clk {
> + compatible = "fixed-factor-clock";
> + #clock-cells = <0>;
> + clocks = <&uclk40xi>;
> + clock-div = <2>;
> + clock-mult = <1>;
> + };
> +
> + pll1: pll1 {
> + compatible =
> + "socionext,milbeaut-m10v-pll-fixed-factor";
> + #clock-cells = <0>;
> + clocks = <&uclk40xi>;
> + offset = <1>;
> + clock-div = <1>;
> + clock-mult = <40>;
> + };
> +
> + pll2: pll2 {
> + compatible =
> + "socionext,milbeaut-m10v-pll-fixed-factor";
> + #clock-cells = <0>;
> + clocks = <&uclk40xi>;
> + offset = <2>;
> + clock-div = <1>;
> + clock-mult = <30>;
> + };
> +
> + pll6: pll6 { /* CLK 6-1 */
> + compatible =
> + "socionext,milbeaut-m10v-pll-fixed-factor";
> + #clock-cells = <0>;
> + clocks = <&uclk40xi>;
> + offset = <7>;
> + clock-div = <1>;
> + clock-mult = <35>;
> + };
> +
> + pll7: pll7 { /* CLK 7-1 */
> + compatible =
> + "socionext,milbeaut-m10v-pll-fixed-factor";
> + #clock-cells = <0>;
> + clocks = <&uclk40xi>;
> + offset = <8>;
> + clock-div = <1>;
> + clock-mult = <40>;
> + };
> +
> + pll9: pll9 { /* CA7CLK, ATCLK */
> + compatible = "fixed-factor-clock";
> + #clock-cells = <0>;
> + clocks = <&uclk40xi>;
> + clock-div = <1>;
> + clock-mult = <33>;
> + };
> +
> + pll10: pll10 {
> + compatible =
> + "socionext,milbeaut-m10v-pll-fixed-factor";
> + #clock-cells = <0>;
> + clocks = <&uclk40xi>;
> + offset = <10>;
> + clock-div = <5>;
> + clock-mult = <108>;
> + };
> +
> + pll11: pll11 { /* CLK 11-1 */
> + compatible =
> + "socionext,milbeaut-m10v-pll-fixed-factor";
> + #clock-cells = <0>;
> + clocks = <&uclk40xi>;
> + offset = <12>;
> + clock-div = <2>;
> + clock-mult = <75>;
> + };
> +
> + emmcclk: emmcclk {
> + compatible = "socionext,milbeaut-m10v-clk-div";
> + #clock-cells = <0>;
> + clocks = <&pll11>;
> + offset = <28>; /* EMMCCLK */
> + mask = <0x3>;
> + ratios = <15 0x7 10 0x6 9 0x5 8 0x4>;
> + };
> +
> + pll1_div_1_2: pll1_div_1_2 { /* CLK 1-2 */
> + compatible = "fixed-factor-clock";
> + #clock-cells = <0>;
> + clocks = <&pll1>;
> + clock-div = <2>;
> + clock-mult = <1>;
> + };
> +
> + pll2_div_1_2: pll2_div_1_2 { /* CLK 2-2 */
> + compatible = "fixed-factor-clock";
> + #clock-cells = <0>;
> + clocks = <&pll2>;
> + clock-div = <2>;
> + clock-mult = <1>;
> + };
> +
> + pll6_div_1_2: pll6_div_1_2 { /* CLK 6-2 */
> + compatible = "fixed-factor-clock";
> + #clock-cells = <0>;
> + clocks = <&pll6>;
> + clock-div = <2>;
> + clock-mult = <1>;
> + };
> +
> + pll6_div_1_3: pll6_div_1_3 { /* CLK 6-3 */
> + compatible = "fixed-factor-clock";
> + #clock-cells = <0>;
> + clocks = <&pll6>;
> + clock-div = <3>;
> + clock-mult = <1>;
> + };
> +
> + pll7_div_1_2: pll7_div_1_2 { /* CLK 7-2 */
> + compatible = "fixed-factor-clock";
> + #clock-cells = <0>;
> + clocks = <&pll7>;
> + clock-div = <2>;
> + clock-mult = <1>;
> + };
> +
> + pll7_div_1_5: pll7_div_1_5 { /* CLK 7-5 */
> + compatible = "fixed-factor-clock";
> + #clock-cells = <0>;
> + clocks = <&pll7>;
> + clock-div = <5>;
> + clock-mult = <1>;
> + };
> +
> + pll10_div_1_2: pll10_div_1_2 { /* CLK 10-2 */
> + compatible = "fixed-factor-clock";
> + #clock-cells = <0>;
> + clocks = <&pll10>;
> + clock-div = <2>;
> + clock-mult = <1>;
> + };
> +
> + spiclk_mux_0: spiclk_mux_0 {
> + compatible = "socionext,milbeaut-m10v-clk-div";
> + #clock-cells = <0>;
> + clocks = <&pll10_div_1_2>;
> + offset = <227>; /* SPICLK */
> + mask = <0x3>;
> + ratios = <4 0x5 2 0x4>;
> + };
> +
> + spiclk_mux_1: spiclk_mux_1 {
> + compatible = "socionext,milbeaut-m10v-clk-div";
> + #clock-cells = <0>;
> + clocks = <&pll7_div_1_2>;
> + offset = <227>; /* SPICLK */
> + mask = <0x3>;
> + ratios = <8 0x6>;
> + };
> +
> + spiclk: spiclk {
> + compatible = "socionext,milbeaut-m10v-clk-mux";
> + #clock-cells = <0>;
> + clocks = <&spiclk_mux_0>, <&spiclk_mux_1>;
> + };
> +
> + ca7wdclk: ca7wdclk {
> + compatible = "fixed-factor-clock";
> + #clock-cells = <0>;
> + clocks = <&pll2_div_1_2>;
> + clock-div = <12>;
> + clock-mult = <1>;
> + };
> +
> + pll9_div_1_2: pll9_div_1_2 {
> + compatible = "fixed-factor-clock";
> + #clock-cells = <0>;
> + clocks = <&pll9>;
> + clock-div = <2>;
> + clock-mult = <1>;
> + };
> +
> + mclk400: mclk400 {
> + compatible = "socionext,milbeaut-m10v-clk-div";
> + #clock-cells = <0>;
> + clocks = <&pll1_div_1_2>;
> + offset = <295>; /* MCLK400 */
> + mask = <0x3>;
> + ratios = <4 0x7 2 0x5>;
> + };
> +
> + mclk200: mclk200 {
> + compatible = "socionext,milbeaut-m10v-clk-div";
> + #clock-cells = <0>;
> + clocks = <&pll1_div_1_2>;
> + offset = <291>; /* MCLK200 */
> + mask = <0x7>;
> + ratios = <8 0xf 4 0xb>;
> + };
> +
> + aclk400: aclk400 {
> + compatible = "socionext,milbeaut-m10v-clk-div";
> + #clock-cells = <0>;
> + clocks = <&pll1_div_1_2>;
> + offset = <288>; /* ACLK400 */
> + mask = <0x3>;
> + ratios = <4 0x7 2 0x5>;
> + };
> +
> + aclk300: aclk300 {
> + compatible = "socionext,milbeaut-m10v-clk-div";
> + #clock-cells = <0>;
> + clocks = <&pll2_div_1_2>;
> + offset = <352>; /* ACLK300 */
> + mask = <0x1>;
> + ratios = <6 0x3 4 0x2>;
> + };
> +
> + aclk: aclk {
> + compatible = "socionext,milbeaut-m10v-clk-div";
> + #clock-cells = <0>;
> + clocks = <&pll1_div_1_2>;
> + offset = <276>; /* ACLK */
> + mask = <0x7>;
> + ratios = <8 0xf 4 0xb>;
> + };
> +
> + aclkexs: aclkexs {
> + compatible = "socionext,milbeaut-m10v-clk-div";
> + #clock-cells = <0>;
> + clocks = <&pll1_div_1_2>;
> + offset = <272>; /* ACLKEXS */
> + mask = <0x7>;
> + ratios = <8 0xf 6 0xd 5 0xc 4 0xb>;
> + };
> +
> + hclk: hclk {
> + compatible = "socionext,milbeaut-m10v-clk-div";
> + #clock-cells = <0>;
> + clocks = <&pll1_div_1_2>;
> + offset = <263>; /* HCLK */
> + mask = <0xf>;
> + ratios = <16 0x1f 8 0x17>;
> + };
> +
> + hclkbmh: hclkbmh {
> + compatible = "socionext,milbeaut-m10v-clk-div";
> + #clock-cells = <0>;
> + clocks = <&pll1_div_1_2>;
> + offset = <268>; /* HCLKBMH */
> + mask = <0x7>;
> + ratios = <8 0xf 4 0xb>;
> + };
> +
> + pclk: pclk {
> + compatible = "socionext,milbeaut-m10v-clk-div";
> + #clock-cells = <0>;
> + clocks = <&pll1_div_1_2>;
> + offset = <256>; /* PCLK */
> + mask = <0x3f>;
> + ratios = <32 0x5f 16 0x4f>;
> + };
> +
> + pclkca7wd: pclkca7wd {
> + compatible = "fixed-factor-clock";
> + #clock-cells = <0>;
> + clocks = <&pll1_div_1_2>;
> + clock-div = <16>;
> + clock-mult = <1>;
> + };
> +
> + rclk: rclk {
> + compatible = "socionext,milbeaut-m10v-clk-div";
> + #clock-cells = <0>;
> + clocks = <&pll10_div_1_2>;
> + offset = <0>; /* RCLK */
> + mask = <0x3>;
> + ratios = <64 0x7 48 0x6 32 0x5 16 0x4>;
> + };
> +
> + uhs1clk0: uhs1clk0 {
> + compatible = "socionext,milbeaut-m10v-clk-div";
> + #clock-cells = <0>;
> + clocks = <&pll7>;
> + offset = <3>; /* UHS1CLK0 */
> + mask = <0xf>;
> + ratios = <16 0x14 8 0x13 4 0x12 3 0x11 2 0x10>;
> + };
> +
> + uhs1clk1_div1: uhs1clk1_div1 {
> + compatible = "socionext,milbeaut-m10v-clk-div";
> + #clock-cells = <0>;
> + clocks = <&pll7>;
> + offset = <8>; /* UHS1CLK1 */
> + mask = <0xf>;
> + ratios = <16 0x14 8 0x13>;
> + };
> +
> + uhs1clk1_div2: uhs1clk1_div2 {
> + compatible = "socionext,milbeaut-m10v-clk-div";
> + #clock-cells = <0>;
> + clocks = <&pll6_div_1_2>;
> + offset = <8>; /* UHS1CLK1 */
> + mask = <0xf>;
> + ratios = <1 0x18>;
> + };
> +
> + uhs1clk1: uhs1clk1 {
> + compatible = "socionext,milbeaut-m10v-clk-mux";
> + #clock-cells = <0>;
> + clocks = <&uhs1clk1_div1>, <&uhs1clk1_div2>;
> + };
> +
> + uhs1clk2_div1: uhs1clk2_div1 {
> + compatible = "socionext,milbeaut-m10v-clk-div";
> + #clock-cells = <0>;
> + clocks = <&pll7>;
> + offset = <13>; /* UHS1CLK2 */
> + mask = <0xf>;
> + ratios = <16 0x14 8 0x13 4 0x12>;
> + };
> +
> + uhs1clk2_div2: uhs1clk2_div2 {
> + compatible = "socionext,milbeaut-m10v-clk-div";
> + #clock-cells = <0>;
> + clocks = <&pll6_div_1_2>;
> + offset = <13>; /* UHS1CLK2 */
> + mask = <0xf>;
> + ratios = <1 0x18>;
> + };
> +
> + uhs1clk2: uhs1clk2 {
> + compatible = "socionext,milbeaut-m10v-clk-mux";
> + #clock-cells = <0>;
> + clocks = <&uhs1clk2_div1>, <&uhs1clk2_div2>;
> + };
> +
> + uhs2clk: uhs2clk {
> + compatible = "socionext,milbeaut-m10v-clk-div";
> + #clock-cells = <0>;
> + clocks = <&pll6_div_1_3>;
> + offset = <18>; /* UHS2CLK */
> + mask = <0x7>;
> + ratios = <18 0xf 16 0xe 14 0xd 13 0xc
> + 12 0xb 11 0xa 10 0x9 9 0x8>;
> + };
> +
> + nfclk_div1: nfclk_div1 {
> + compatible = "socionext,milbeaut-m10v-clk-div";
> + #clock-cells = <0>;
> + clocks = <&pll7_div_1_2>;
> + offset = <22>; /* NFCLK */
> + mask = <0x1f>;
> + ratios = <40 0x24 16 0x23 13 0x22 10 0x21
> + 8 0x20>;
> + };
> +
> + nfclk_div2: nfclk_div2 {
> + compatible = "socionext,milbeaut-m10v-clk-div";
> + #clock-cells = <0>;
> + clocks = <&pll7_div_1_5>;
> + offset = <22>; /* NFCLK */
> + mask = <0x1f>;
> + ratios = <10 0x28>;
> + };
> +
> + nfclk: nfclk {
> + compatible = "socionext,milbeaut-m10v-clk-mux";
> + #clock-cells = <0>;
> + clocks = <&nfclk_div1>, <&nfclk_div2>;
> + };
> +
> + clk5: clk5 {
> + compatible = "socionext,milbeaut-m10v-clk-div";
> + #clock-cells = <0>;
> + clocks = <&pll10_div_1_2>;
> + offset = <239>; /* NETAUSEL */
> + mask = <0x3>;
> + ratios = <64 0x7 48 0x6 32 0x5 16 0x4>;
> + };
> + };
> + };
> +
> + peri-timer@1e000000 { /* 32-bit Reload Timers */
timer@1e000050
This and all memory mapped peripherals go under simple-bus nodes(s).
> + compatible = "socionext,milbeaut-m10v-timer";
> + reg = <0x1e000050 0x10>, <0x1e000060 0x10>;
> + interrupts = <0 91 4>;
> + clocks = <&rclk>;
> + };
> +
> + timer { /* The Generic Timer */
> + compatible = "arm,armv7-timer";
> + interrupts = <GIC_PPI 13
> + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
> + <GIC_PPI 14
> + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
> + <GIC_PPI 11
> + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
> + <GIC_PPI 10
> + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
> + clock-frequency = <40000000>;//40M
> + always-on;
> + arm,cpu-registers-not-fw-configured;
This was a work-around for some existing platforms. New platforms
should fix the firmware/bootloader.
> + };
> +
> + dummy_clk: dummy_clk {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <50000000>;
> + };
> +
> + pinctrl: pinctrl@1d022000 {
> + compatible = "socionext,milbeaut-m10v-pinctrl";
> + reg = <0x1d022000 0x1000>,
> + <0x1c26f000 0x1000>;
> + reg-names = "pinctrl", "exiu";
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + clocks = <&dummy_clk>;
Please use a real clock or make clocks optional.
> + interrupts = <0 54 4>, <0 55 4>, <0 56 4>, <0 57 4>,
> + <0 58 4>, <0 59 4>, <0 60 4>, <0 61 4>,
> + <0 62 4>, <0 63 4>, <0 64 4>, <0 65 4>,
> + <0 66 4>, <0 67 4>, <0 68 4>, <0 69 4>;
> + interrupt-names = "pin-48", "pin-49", "pin-50", "pin-51",
> + "pin-52", "pin-53", "pin-54", "pin-55",
> + "pin-56", "pin-57", "pin-58", "pin-59",
> + "pin-60", "pin-61", "pin-62", "pin-63";
> +
> + usio1_pins: usio1_pins {
> + pins = "PE4", "PE5", "P87";
> + function = "usio1";
> + };
> + };
> +
> + usio1: usio_uart@1e700010 { /* PE4, PE5 */
serial@...
> + /* Enable this as ttyUSI0 */
> + index = <0>;
Drop this. aliases node is the right way to do this.
> + compatible = "socionext,milbeaut-m10v-usio-uart";
> + reg = <0x1e700010 0x10>;
> + interrupts = <0 141 0x4>, <0 149 0x4>;
> + interrupt-names = "rx", "tx";
> + clocks = <&hclk>;
> + };
> +};
> --
> 1.9.1
>
^ permalink raw reply [flat|nested] 11+ messages in thread
* RE: [PATCH 12/14] ARM: dts: milbeaut: Add device tree set for the Milbeaut M10V board
2018-11-19 15:46 ` Rob Herring
@ 2018-11-21 2:36 ` sugaya.taichi
0 siblings, 0 replies; 11+ messages in thread
From: sugaya.taichi @ 2018-11-21 2:36 UTC (permalink / raw)
To: robh+dt, arm
Cc: linux-clk, devicetree, linux-arm-kernel, linux-kernel,
linux-serial, mturquette, sboyd, mark.rutland, gregkh,
daniel.lezcano, tglx, linux, jslaby, masami.hiramatsu,
jaswinder.singh
Hi Rob
Thank you for your comments.
> -----Original Message-----
> From: Rob Herring [mailto:robh+dt@kernel.org]
> Sent: Tuesday, November 20, 2018 12:46 AM
> To: Sugaya, Taichi; ARM-SoC Maintainers
> Cc: linux-clk; devicetree@vger.kernel.org; moderated list:ARM/FREESCALE
> IMX / MXC ARM ARCHITECTURE; linux-kernel@vger.kernel.org; open list:SERIAL
> DRIVERS; Michael Turquette; Stephen Boyd; Mark Rutland; Greg Kroah-Hartman;
> Daniel Lezcano; Thomas Gleixner; Russell King; Jiri Slaby; Masami Hiramatsu;
> Jassi Brar
> Subject: Re: [PATCH 12/14] ARM: dts: milbeaut: Add device tree set for the
> Milbeaut M10V board
>
> On Sun, Nov 18, 2018 at 7:01 PM Sugaya Taichi
> <sugaya.taichi@socionext.com> wrote:
> >
> > Add devicetree for Milbeaut M10V SoC and M10V Evaluation board.
> >
> > Signed-off-by: Sugaya Taichi <sugaya.taichi@socionext.com>
> > ---
> > arch/arm/boot/dts/Makefile | 1 +
> > arch/arm/boot/dts/milbeaut-m10v-evb.dts | 35 +++
> > arch/arm/boot/dts/milbeaut-m10v-evb.dtsi | 17 ++
> > arch/arm/boot/dts/milbeaut-m10v.dtsi | 510
> +++++++++++++++++++++++++++++++
>
> I'm not seeing why you need this split into 3 files instead of 2.
Correct...
Modify using 2 files.
>
> > 4 files changed, 563 insertions(+)
> > create mode 100644 arch/arm/boot/dts/milbeaut-m10v-evb.dts
> > create mode 100644 arch/arm/boot/dts/milbeaut-m10v-evb.dtsi
> > create mode 100644 arch/arm/boot/dts/milbeaut-m10v.dtsi
>
> Build your dtb with 'W=12' and fix any warnings.
Ah, I may have missed warnings. will confirm and fix them.
>
> >
> > diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> > index b0e966d..ee6220b 100644
> > --- a/arch/arm/boot/dts/Makefile
> > +++ b/arch/arm/boot/dts/Makefile
> > @@ -1207,6 +1207,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
> > mt7623n-bananapi-bpi-r2.dtb \
> > mt8127-moose.dtb \
> > mt8135-evbp1.dtb
> > +dtb-$(CONFIG_MACH_M10V_EVB) += milbeaut-m10v-evb.dtb
>
> ARM SoC maintainers,
>
> Can we start at least start putting new SoCs in vendor subdirs? This
> one doesn't appear to share anything.
>
> > dtb-$(CONFIG_ARCH_ZX) += zx296702-ad1.dtb
> > dtb-$(CONFIG_ARCH_ASPEED) += \
> > aspeed-ast2500-evb.dtb \
> > diff --git a/arch/arm/boot/dts/milbeaut-m10v-evb.dts
> b/arch/arm/boot/dts/milbeaut-m10v-evb.dts
> > new file mode 100644
> > index 0000000..af8d6e4
> > --- /dev/null
> > +++ b/arch/arm/boot/dts/milbeaut-m10v-evb.dts
> > @@ -0,0 +1,35 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/* Socionext Milbeaut M10V Evaluation Board */
> > +/dts-v1/;
> > +#include "milbeaut-m10v-evb.dtsi"
> > +
> > +/ {
> > + cpus {
>
> cpus is not board specific.
Yes..
Cpus Should be described in "milbeaut-m10v-evb.dtsi".
>
> > + cpu@0 {
>
> Unit-address is wrong. Should be '@f00' to match reg.
Ok.
>
> > + device_type = "cpu";
> > + compatible = "arm,cortex-a7";
> > + reg = <0xf00>;
> > + };
> > + cpu@1 {
> > + device_type = "cpu";
> > + compatible = "arm,cortex-a7";
> > + reg = <0xf01>;
> > + };
> > +
> > + cpu@2 {
> > + device_type = "cpu";
> > + compatible = "arm,cortex-a7";
> > + reg = <0xf02>;
> > + };
> > + cpu@3 {
> > + device_type = "cpu";
> > + compatible = "arm,cortex-a7";
> > + reg = <0xf03>;
> > + };
> > +
> > + };
> > + trampoline: trampoline@0x0000F100 {
>
> Also, not board specific.
>
> This should be under a simple-bus node. The unit-address should be '@f100'.
>
> > + compatible = "socionext,smp-trampoline";
> > + reg = <0x0000F100 0x100>;
>
> Use lowercase hex.
OKay.
>
> > + };
> > +};
> > diff --git a/arch/arm/boot/dts/milbeaut-m10v-evb.dtsi
> b/arch/arm/boot/dts/milbeaut-m10v-evb.dtsi
> > new file mode 100644
> > index 0000000..fc35c0b
> > --- /dev/null
> > +++ b/arch/arm/boot/dts/milbeaut-m10v-evb.dtsi
> > @@ -0,0 +1,17 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +#include "milbeaut-m10v.dtsi"
> > +
> > +/ {
> > + model = "Socionext M10V EVB";
> > + compatible = "socionext,sc2000a",
> "socionext,milbeaut-m10v-evb";
>
> Wrong order. And these need to be documented.
I got it.
>
> > + interrupt-parent = <&gic>;
> > + chosen {
> > + bootargs = "consoleblank=0 loglevel=8 init=/sbin/finit
> root=/dev/mmcblk0p2 rootwait ro console=ttyUSI0,115200n8
> console=/dev/tty1 ";
>
> Most of these options look user specific and should be dropped. Use
> 'stdout-path' to specify the default console.
OK, try to use it.
>
> > + linux,initrd-start = <0x4A000000>;
> > + linux,initrd-end = <0x4BF00000>;
>
> initrd should be filled in by the bootloader.
OK.
>
> > + };
> > + memory {
>
> Needs a unit-address.
OK.
>
> > + device_type = "memory";
> > + reg = <0x40000000 0x80000000>;
> > + };
> > +};
> > diff --git a/arch/arm/boot/dts/milbeaut-m10v.dtsi
> b/arch/arm/boot/dts/milbeaut-m10v.dtsi
> > new file mode 100644
> > index 0000000..4745dc6
> > --- /dev/null
> > +++ b/arch/arm/boot/dts/milbeaut-m10v.dtsi
> > @@ -0,0 +1,510 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +#include <dt-bindings/interrupt-controller/irq.h>
> > +#include <dt-bindings/input/input.h>
> > +#include <dt-bindings/gpio/gpio.h>
> > +#include <dt-bindings/interrupt-controller/arm-gic.h>
> > +
> > +#include "skeleton.dtsi"
>
> Don't use skeleton.dtsi. It is deprecated.
I got it. Get rid of it.
>
> > +
> > +/ {
> > + compatible = "socionext,sc2000a";
> > + interrupt-parent = <&gic>;
> > + cpus {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + };
>
> Just move this to the other file with the cpu nodes.
I see.
I'd like to select the way to move the cpu nodes to this file.
>
> > +
> > +
> > + gic: interrupt-controller@1d000000 {
> > + compatible = "arm,cortex-a7-gic";
> > + interrupt-controller;
> > + #interrupt-cells = <3>;
> > + reg = <0x1d001000 0x1000>, /* Distributer base and size
> */
> > + <0x1d002000 0x1000>; /* CPU I/f base and size */
> > + };
> > +
> > + m10v-clk-tree@ {
>
> unit-address
OK, add it.
>
> > + compatible = "socionext,milbeaut-m10v-clk-regs";
> > + reg = <0x1d021000 0x4000>;
> > +
> > + clocks {
> > + #address-cells = <0>;
> > + #size-cells = <0>;
> > +
> > + uclk40xi: uclk40xi {
> > + compatible = "fixed-clock";
> > + #clock-cells = <0>;
> > + clock-frequency = <40000000>;
> > + };
>
> Any fixed clocks from oscillators on the board should be at the top
> level and defined as inputs to the clock controller node with a
> 'clocks' property.
OK.
>
> > +
> > + aumclki: aumclki {
> > + compatible = "fixed-clock";
> > + #clock-cells = <0>;
> > + clock-frequency = <20000000>;
> > + };
> > +
> > + rtc32k: rtc32k {
> > + compatible = "fixed-clock";
> > + #clock-cells = <0>;
> > + clock-frequency = <32768>;
> > + };
> > +
> > + pxrefclk: pxrefclk {
> > + compatible = "fixed-clock";
> > + #clock-cells = <0>;
> > + clock-frequency = <100000000>;
> > + };
> > +
> > + pcisuppclk: pcisuppclk {
> > + compatible = "fixed-factor-clock";
> > + #clock-cells = <0>;
> > + clocks = <&uclk40xi>;
> > + clock-div = <20>;
> > + clock-mult = <1>;
> > + };
>
> Please look at any recent example of clock bindings. We don't try to
> describe every divider, mux, gate, etc. in DT, but just clock
> controller blocks with all the output clocks enumerated in clock
> cells.
OK, study them at first.
>
> > +
> > + usb2_clk: usb2_clk {
> > + compatible = "fixed-factor-clock";
> > + #clock-cells = <0>;
> > + clocks = <&uclk40xi>;
> > + clock-div = <2>;
> > + clock-mult = <1>;
> > + };
> > +
> > + pll1: pll1 {
> > + compatible =
> > +
> "socionext,milbeaut-m10v-pll-fixed-factor";
> > + #clock-cells = <0>;
> > + clocks = <&uclk40xi>;
> > + offset = <1>;
> > + clock-div = <1>;
> > + clock-mult = <40>;
> > + };
> > +
> > + pll2: pll2 {
> > + compatible =
> > +
> "socionext,milbeaut-m10v-pll-fixed-factor";
> > + #clock-cells = <0>;
> > + clocks = <&uclk40xi>;
> > + offset = <2>;
> > + clock-div = <1>;
> > + clock-mult = <30>;
> > + };
> > +
> > + pll6: pll6 { /* CLK 6-1 */
> > + compatible =
> > +
> "socionext,milbeaut-m10v-pll-fixed-factor";
> > + #clock-cells = <0>;
> > + clocks = <&uclk40xi>;
> > + offset = <7>;
> > + clock-div = <1>;
> > + clock-mult = <35>;
> > + };
> > +
> > + pll7: pll7 { /* CLK 7-1 */
> > + compatible =
> > +
> "socionext,milbeaut-m10v-pll-fixed-factor";
> > + #clock-cells = <0>;
> > + clocks = <&uclk40xi>;
> > + offset = <8>;
> > + clock-div = <1>;
> > + clock-mult = <40>;
> > + };
> > +
> > + pll9: pll9 { /* CA7CLK, ATCLK */
> > + compatible = "fixed-factor-clock";
> > + #clock-cells = <0>;
> > + clocks = <&uclk40xi>;
> > + clock-div = <1>;
> > + clock-mult = <33>;
> > + };
> > +
> > + pll10: pll10 {
> > + compatible =
> > +
> "socionext,milbeaut-m10v-pll-fixed-factor";
> > + #clock-cells = <0>;
> > + clocks = <&uclk40xi>;
> > + offset = <10>;
> > + clock-div = <5>;
> > + clock-mult = <108>;
> > + };
> > +
> > + pll11: pll11 { /* CLK 11-1 */
> > + compatible =
> > +
> "socionext,milbeaut-m10v-pll-fixed-factor";
> > + #clock-cells = <0>;
> > + clocks = <&uclk40xi>;
> > + offset = <12>;
> > + clock-div = <2>;
> > + clock-mult = <75>;
> > + };
> > +
> > + emmcclk: emmcclk {
> > + compatible =
> "socionext,milbeaut-m10v-clk-div";
> > + #clock-cells = <0>;
> > + clocks = <&pll11>;
> > + offset = <28>; /* EMMCCLK */
> > + mask = <0x3>;
> > + ratios = <15 0x7 10 0x6 9 0x5 8 0x4>;
> > + };
> > +
> > + pll1_div_1_2: pll1_div_1_2 { /* CLK 1-2 */
> > + compatible = "fixed-factor-clock";
> > + #clock-cells = <0>;
> > + clocks = <&pll1>;
> > + clock-div = <2>;
> > + clock-mult = <1>;
> > + };
> > +
> > + pll2_div_1_2: pll2_div_1_2 { /* CLK 2-2 */
> > + compatible = "fixed-factor-clock";
> > + #clock-cells = <0>;
> > + clocks = <&pll2>;
> > + clock-div = <2>;
> > + clock-mult = <1>;
> > + };
> > +
> > + pll6_div_1_2: pll6_div_1_2 { /* CLK 6-2 */
> > + compatible = "fixed-factor-clock";
> > + #clock-cells = <0>;
> > + clocks = <&pll6>;
> > + clock-div = <2>;
> > + clock-mult = <1>;
> > + };
> > +
> > + pll6_div_1_3: pll6_div_1_3 { /* CLK 6-3 */
> > + compatible = "fixed-factor-clock";
> > + #clock-cells = <0>;
> > + clocks = <&pll6>;
> > + clock-div = <3>;
> > + clock-mult = <1>;
> > + };
> > +
> > + pll7_div_1_2: pll7_div_1_2 { /* CLK 7-2 */
> > + compatible = "fixed-factor-clock";
> > + #clock-cells = <0>;
> > + clocks = <&pll7>;
> > + clock-div = <2>;
> > + clock-mult = <1>;
> > + };
> > +
> > + pll7_div_1_5: pll7_div_1_5 { /* CLK 7-5 */
> > + compatible = "fixed-factor-clock";
> > + #clock-cells = <0>;
> > + clocks = <&pll7>;
> > + clock-div = <5>;
> > + clock-mult = <1>;
> > + };
> > +
> > + pll10_div_1_2: pll10_div_1_2 { /* CLK 10-2 */
> > + compatible = "fixed-factor-clock";
> > + #clock-cells = <0>;
> > + clocks = <&pll10>;
> > + clock-div = <2>;
> > + clock-mult = <1>;
> > + };
> > +
> > + spiclk_mux_0: spiclk_mux_0 {
> > + compatible =
> "socionext,milbeaut-m10v-clk-div";
> > + #clock-cells = <0>;
> > + clocks = <&pll10_div_1_2>;
> > + offset = <227>; /* SPICLK */
> > + mask = <0x3>;
> > + ratios = <4 0x5 2 0x4>;
> > + };
> > +
> > + spiclk_mux_1: spiclk_mux_1 {
> > + compatible =
> "socionext,milbeaut-m10v-clk-div";
> > + #clock-cells = <0>;
> > + clocks = <&pll7_div_1_2>;
> > + offset = <227>; /* SPICLK */
> > + mask = <0x3>;
> > + ratios = <8 0x6>;
> > + };
> > +
> > + spiclk: spiclk {
> > + compatible =
> "socionext,milbeaut-m10v-clk-mux";
> > + #clock-cells = <0>;
> > + clocks = <&spiclk_mux_0>,
> <&spiclk_mux_1>;
> > + };
> > +
> > + ca7wdclk: ca7wdclk {
> > + compatible = "fixed-factor-clock";
> > + #clock-cells = <0>;
> > + clocks = <&pll2_div_1_2>;
> > + clock-div = <12>;
> > + clock-mult = <1>;
> > + };
> > +
> > + pll9_div_1_2: pll9_div_1_2 {
> > + compatible = "fixed-factor-clock";
> > + #clock-cells = <0>;
> > + clocks = <&pll9>;
> > + clock-div = <2>;
> > + clock-mult = <1>;
> > + };
> > +
> > + mclk400: mclk400 {
> > + compatible =
> "socionext,milbeaut-m10v-clk-div";
> > + #clock-cells = <0>;
> > + clocks = <&pll1_div_1_2>;
> > + offset = <295>; /* MCLK400 */
> > + mask = <0x3>;
> > + ratios = <4 0x7 2 0x5>;
> > + };
> > +
> > + mclk200: mclk200 {
> > + compatible =
> "socionext,milbeaut-m10v-clk-div";
> > + #clock-cells = <0>;
> > + clocks = <&pll1_div_1_2>;
> > + offset = <291>; /* MCLK200 */
> > + mask = <0x7>;
> > + ratios = <8 0xf 4 0xb>;
> > + };
> > +
> > + aclk400: aclk400 {
> > + compatible =
> "socionext,milbeaut-m10v-clk-div";
> > + #clock-cells = <0>;
> > + clocks = <&pll1_div_1_2>;
> > + offset = <288>; /* ACLK400 */
> > + mask = <0x3>;
> > + ratios = <4 0x7 2 0x5>;
> > + };
> > +
> > + aclk300: aclk300 {
> > + compatible =
> "socionext,milbeaut-m10v-clk-div";
> > + #clock-cells = <0>;
> > + clocks = <&pll2_div_1_2>;
> > + offset = <352>; /* ACLK300 */
> > + mask = <0x1>;
> > + ratios = <6 0x3 4 0x2>;
> > + };
> > +
> > + aclk: aclk {
> > + compatible =
> "socionext,milbeaut-m10v-clk-div";
> > + #clock-cells = <0>;
> > + clocks = <&pll1_div_1_2>;
> > + offset = <276>; /* ACLK */
> > + mask = <0x7>;
> > + ratios = <8 0xf 4 0xb>;
> > + };
> > +
> > + aclkexs: aclkexs {
> > + compatible =
> "socionext,milbeaut-m10v-clk-div";
> > + #clock-cells = <0>;
> > + clocks = <&pll1_div_1_2>;
> > + offset = <272>; /* ACLKEXS */
> > + mask = <0x7>;
> > + ratios = <8 0xf 6 0xd 5 0xc 4 0xb>;
> > + };
> > +
> > + hclk: hclk {
> > + compatible =
> "socionext,milbeaut-m10v-clk-div";
> > + #clock-cells = <0>;
> > + clocks = <&pll1_div_1_2>;
> > + offset = <263>; /* HCLK */
> > + mask = <0xf>;
> > + ratios = <16 0x1f 8 0x17>;
> > + };
> > +
> > + hclkbmh: hclkbmh {
> > + compatible =
> "socionext,milbeaut-m10v-clk-div";
> > + #clock-cells = <0>;
> > + clocks = <&pll1_div_1_2>;
> > + offset = <268>; /* HCLKBMH */
> > + mask = <0x7>;
> > + ratios = <8 0xf 4 0xb>;
> > + };
> > +
> > + pclk: pclk {
> > + compatible =
> "socionext,milbeaut-m10v-clk-div";
> > + #clock-cells = <0>;
> > + clocks = <&pll1_div_1_2>;
> > + offset = <256>; /* PCLK */
> > + mask = <0x3f>;
> > + ratios = <32 0x5f 16 0x4f>;
> > + };
> > +
> > + pclkca7wd: pclkca7wd {
> > + compatible = "fixed-factor-clock";
> > + #clock-cells = <0>;
> > + clocks = <&pll1_div_1_2>;
> > + clock-div = <16>;
> > + clock-mult = <1>;
> > + };
> > +
> > + rclk: rclk {
> > + compatible =
> "socionext,milbeaut-m10v-clk-div";
> > + #clock-cells = <0>;
> > + clocks = <&pll10_div_1_2>;
> > + offset = <0>; /* RCLK */
> > + mask = <0x3>;
> > + ratios = <64 0x7 48 0x6 32 0x5 16 0x4>;
> > + };
> > +
> > + uhs1clk0: uhs1clk0 {
> > + compatible =
> "socionext,milbeaut-m10v-clk-div";
> > + #clock-cells = <0>;
> > + clocks = <&pll7>;
> > + offset = <3>; /* UHS1CLK0 */
> > + mask = <0xf>;
> > + ratios = <16 0x14 8 0x13 4 0x12 3 0x11
> 2 0x10>;
> > + };
> > +
> > + uhs1clk1_div1: uhs1clk1_div1 {
> > + compatible =
> "socionext,milbeaut-m10v-clk-div";
> > + #clock-cells = <0>;
> > + clocks = <&pll7>;
> > + offset = <8>; /* UHS1CLK1 */
> > + mask = <0xf>;
> > + ratios = <16 0x14 8 0x13>;
> > + };
> > +
> > + uhs1clk1_div2: uhs1clk1_div2 {
> > + compatible =
> "socionext,milbeaut-m10v-clk-div";
> > + #clock-cells = <0>;
> > + clocks = <&pll6_div_1_2>;
> > + offset = <8>; /* UHS1CLK1 */
> > + mask = <0xf>;
> > + ratios = <1 0x18>;
> > + };
> > +
> > + uhs1clk1: uhs1clk1 {
> > + compatible =
> "socionext,milbeaut-m10v-clk-mux";
> > + #clock-cells = <0>;
> > + clocks = <&uhs1clk1_div1>,
> <&uhs1clk1_div2>;
> > + };
> > +
> > + uhs1clk2_div1: uhs1clk2_div1 {
> > + compatible =
> "socionext,milbeaut-m10v-clk-div";
> > + #clock-cells = <0>;
> > + clocks = <&pll7>;
> > + offset = <13>; /* UHS1CLK2 */
> > + mask = <0xf>;
> > + ratios = <16 0x14 8 0x13 4 0x12>;
> > + };
> > +
> > + uhs1clk2_div2: uhs1clk2_div2 {
> > + compatible =
> "socionext,milbeaut-m10v-clk-div";
> > + #clock-cells = <0>;
> > + clocks = <&pll6_div_1_2>;
> > + offset = <13>; /* UHS1CLK2 */
> > + mask = <0xf>;
> > + ratios = <1 0x18>;
> > + };
> > +
> > + uhs1clk2: uhs1clk2 {
> > + compatible =
> "socionext,milbeaut-m10v-clk-mux";
> > + #clock-cells = <0>;
> > + clocks = <&uhs1clk2_div1>,
> <&uhs1clk2_div2>;
> > + };
> > +
> > + uhs2clk: uhs2clk {
> > + compatible =
> "socionext,milbeaut-m10v-clk-div";
> > + #clock-cells = <0>;
> > + clocks = <&pll6_div_1_3>;
> > + offset = <18>; /* UHS2CLK */
> > + mask = <0x7>;
> > + ratios = <18 0xf 16 0xe 14 0xd 13 0xc
> > + 12 0xb 11 0xa 10 0x9 9
> 0x8>;
> > + };
> > +
> > + nfclk_div1: nfclk_div1 {
> > + compatible =
> "socionext,milbeaut-m10v-clk-div";
> > + #clock-cells = <0>;
> > + clocks = <&pll7_div_1_2>;
> > + offset = <22>; /* NFCLK */
> > + mask = <0x1f>;
> > + ratios = <40 0x24 16 0x23 13 0x22 10 0x21
> > + 8 0x20>;
> > + };
> > +
> > + nfclk_div2: nfclk_div2 {
> > + compatible =
> "socionext,milbeaut-m10v-clk-div";
> > + #clock-cells = <0>;
> > + clocks = <&pll7_div_1_5>;
> > + offset = <22>; /* NFCLK */
> > + mask = <0x1f>;
> > + ratios = <10 0x28>;
> > + };
> > +
> > + nfclk: nfclk {
> > + compatible =
> "socionext,milbeaut-m10v-clk-mux";
> > + #clock-cells = <0>;
> > + clocks = <&nfclk_div1>, <&nfclk_div2>;
> > + };
> > +
> > + clk5: clk5 {
> > + compatible =
> "socionext,milbeaut-m10v-clk-div";
> > + #clock-cells = <0>;
> > + clocks = <&pll10_div_1_2>;
> > + offset = <239>; /* NETAUSEL */
> > + mask = <0x3>;
> > + ratios = <64 0x7 48 0x6 32 0x5 16 0x4>;
> > + };
> > + };
> > + };
> > +
> > + peri-timer@1e000000 { /* 32-bit Reload Timers */
>
> timer@1e000050
>
> This and all memory mapped peripherals go under simple-bus nodes(s).
Okay.
>
> > + compatible = "socionext,milbeaut-m10v-timer";
> > + reg = <0x1e000050 0x10>, <0x1e000060 0x10>;
> > + interrupts = <0 91 4>;
> > + clocks = <&rclk>;
> > + };
> > +
> > + timer { /* The Generic Timer */
> > + compatible = "arm,armv7-timer";
> > + interrupts = <GIC_PPI 13
> > + (GIC_CPU_MASK_SIMPLE(4) |
> IRQ_TYPE_LEVEL_HIGH)>,
> > + <GIC_PPI 14
> > + (GIC_CPU_MASK_SIMPLE(4) |
> IRQ_TYPE_LEVEL_HIGH)>,
> > + <GIC_PPI 11
> > + (GIC_CPU_MASK_SIMPLE(4) |
> IRQ_TYPE_LEVEL_HIGH)>,
> > + <GIC_PPI 10
> > + (GIC_CPU_MASK_SIMPLE(4) |
> IRQ_TYPE_LEVEL_HIGH)>;
> > + clock-frequency = <40000000>;//40M
> > + always-on;
> > + arm,cpu-registers-not-fw-configured;
>
> This was a work-around for some existing platforms. New platforms
> should fix the firmware/bootloader.
OK. try to fix without the property.
>
> > + };
> > +
> > + dummy_clk: dummy_clk {
> > + compatible = "fixed-clock";
> > + #clock-cells = <0>;
> > + clock-frequency = <50000000>;
> > + };
> > +
> > + pinctrl: pinctrl@1d022000 {
> > + compatible = "socionext,milbeaut-m10v-pinctrl";
> > + reg = <0x1d022000 0x1000>,
> > + <0x1c26f000 0x1000>;
> > + reg-names = "pinctrl", "exiu";
> > + gpio-controller;
> > + #gpio-cells = <2>;
> > + interrupt-controller;
> > + #interrupt-cells = <2>;
> > + clocks = <&dummy_clk>;
>
> Please use a real clock or make clocks optional.
OK.
>
> > + interrupts = <0 54 4>, <0 55 4>, <0 56 4>, <0 57 4>,
> > + <0 58 4>, <0 59 4>, <0 60 4>, <0 61 4>,
> > + <0 62 4>, <0 63 4>, <0 64 4>, <0 65 4>,
> > + <0 66 4>, <0 67 4>, <0 68 4>, <0 69 4>;
> > + interrupt-names = "pin-48", "pin-49", "pin-50",
> "pin-51",
> > + "pin-52", "pin-53", "pin-54", "pin-55",
> > + "pin-56", "pin-57", "pin-58", "pin-59",
> > + "pin-60", "pin-61", "pin-62", "pin-63";
> > +
> > + usio1_pins: usio1_pins {
> > + pins = "PE4", "PE5", "P87";
> > + function = "usio1";
> > + };
> > + };
> > +
> > + usio1: usio_uart@1e700010 { /* PE4, PE5 */
>
> serial@...
OK.
>
> > + /* Enable this as ttyUSI0 */
> > + index = <0>;
>
> Drop this. aliases node is the right way to do this.
I see. try to use the way.
Thanks
Sugaya Taichi
>
> > + compatible = "socionext,milbeaut-m10v-usio-uart";
> > + reg = <0x1e700010 0x10>;
> > + interrupts = <0 141 0x4>, <0 149 0x4>;
> > + interrupt-names = "rx", "tx";
> > + clocks = <&hclk>;
> > + };
> > +};
> > --
> > 1.9.1
> >
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 11/14] pinctrl: milbeaut: Add Milbeaut M10V pinctrl
2018-11-19 1:02 ` [PATCH 11/14] pinctrl: milbeaut: Add Milbeaut M10V pinctrl Sugaya Taichi
@ 2018-12-04 11:23 ` Masahiro Yamada
2018-12-05 5:03 ` Sugaya, Taichi
0 siblings, 1 reply; 11+ messages in thread
From: Masahiro Yamada @ 2018-12-04 11:23 UTC (permalink / raw)
To: sugaya.taichi
Cc: linux-clk, DTML, linux-arm-kernel, Linux Kernel Mailing List,
linux-serial, Michael Turquette, Stephen Boyd, Rob Herring,
Mark Rutland, Greg Kroah-Hartman, Daniel Lezcano,
Thomas Gleixner, Russell King, Jiri Slaby, Masami Hiramatsu,
Jassi Brar
Hi Sugaya-san
On Mon, Nov 19, 2018 at 10:01 AM Sugaya Taichi
<sugaya.taichi@socionext.com> wrote:
>
> Add Milbeaut M10V pinctrl.
> The M10V has the pins that can be used GPIOs or take multiple other
> functions.
>
> Signed-off-by: Sugaya Taichi <sugaya.taichi@socionext.com>
This patch was sent to:
linux-clk@vger.kernel.org,
devicetree@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org,
linux-serial@vger.kernel.org
Unfortunately, the most important ML
linux-gpio@vger.kernel.org
was not addressed.
The pinctrl maintainer may not notice this patch.
> diff --git a/drivers/pinctrl/pinctrl-m10v.c b/drivers/pinctrl/pinctrl-m10v.c
> new file mode 100644
> index 0000000..d4ca713
> --- /dev/null
> +++ b/drivers/pinctrl/pinctrl-m10v.c
> @@ -0,0 +1,765 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2018 Socionext Ltd.
> + * Copyright (C) 2015 Linaro Ltd.
> + * Author: Jassi Brar <jaswinder.singh@linaro.org>
My company name is "Socionext Inc." instead of "Socionext Ltd."
> +static struct platform_driver m10v_pinctrl_driver = {
> + .probe = m10v_pinctrl_probe,
> + .driver = {
> + .name = "m10v-pinctrl",
> + .of_match_table = m10v_pmatch,
> + },
> +};
> +
> +static int __init m10v_pinctrl_init(void)
> +{
> + return platform_driver_register(&m10v_pinctrl_driver);
> +}
> +arch_initcall(m10v_pinctrl_init);
Can't it be builtin_platform_driver()?
Which device requires this to be arch_initcall()?
--
Best Regards
Masahiro Yamada
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 10/14] dt-bindings: pinctrl: milbeaut: Add Milbeaut M10V pinctrl description
2018-11-19 1:02 [PATCH 10/14] dt-bindings: pinctrl: milbeaut: Add Milbeaut M10V pinctrl description Sugaya Taichi
` (3 preceding siblings ...)
2018-11-19 1:02 ` [PATCH 14/14] MAINTAINERS: Add entry to MAINTAINERS for Milbeaut Sugaya Taichi
@ 2018-12-04 23:11 ` Rob Herring
2018-12-06 8:29 ` Sugaya, Taichi
4 siblings, 1 reply; 11+ messages in thread
From: Rob Herring @ 2018-12-04 23:11 UTC (permalink / raw)
To: Sugaya Taichi
Cc: linux-clk, devicetree, linux-arm-kernel, linux-kernel,
linux-serial, Michael Turquette, Stephen Boyd, Mark Rutland,
Greg Kroah-Hartman, Daniel Lezcano, Thomas Gleixner,
Russell King, Jiri Slaby, Masami Hiramatsu, Jassi Brar
On Mon, Nov 19, 2018 at 10:02:12AM +0900, Sugaya Taichi wrote:
> Add DT bindings document for Milbeaut M10V pinctrl.
>
> Signed-off-by: Sugaya Taichi <sugaya.taichi@socionext.com>
> ---
> .../pinctrl/socionext,milbeaut-pinctrl.txt | 33 ++++++++++++++++++++++
> 1 file changed, 33 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/pinctrl/socionext,milbeaut-pinctrl.txt
>
> diff --git a/Documentation/devicetree/bindings/pinctrl/socionext,milbeaut-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/socionext,milbeaut-pinctrl.txt
> new file mode 100644
> index 0000000..7469189
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pinctrl/socionext,milbeaut-pinctrl.txt
> @@ -0,0 +1,33 @@
> +Milbeaut SoCs pin controller
> +
> +Required properties:
> +- compatible: should be one of the following:
> + "socionext,milbeaut-m10v-pinctrl" - for m10v SoC
> +- reg: offset and length of the register set.
> +- reg-names: should be "pinctrl", "exiu".
> +- gpio-cells; should be 2.
#gpio-cells
gpio-controller?
> +- interrupt-cells: should be 2.
#interrupt-cells
interrupt-controller?
> +- clocks: phandle to the input clock.
> +- interrupts: three interrupts specifer.
> +- interrupt-names: corresponds "interrupts" factor.
> +
> +Example:
> + pinctrl: pinctrl@1d022000 {
> + compatible = "socionext,milbeaut-m10v-pinctrl";
> + reg = <0x1d022000 0x1000>,
> + <0x1c26f000 0x1000>;
> + reg-names = "pinctrl", "exiu";
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + clocks = <&dummy_clk>;
> + interrupts = <0 54 4>, <0 55 4>, <0 56 4>, <0 57 4>,
> + <0 58 4>, <0 59 4>, <0 60 4>, <0 61 4>,
> + <0 62 4>, <0 63 4>, <0 64 4>, <0 65 4>,
> + <0 66 4>, <0 67 4>, <0 68 4>, <0 69 4>;
> + interrupt-names = "pin-48", "pin-49", "pin-50", "pin-51",
> + "pin-52", "pin-53", "pin-54", "pin-55",
> + "pin-56", "pin-57", "pin-58", "pin-59",
> + "pin-60", "pin-61", "pin-62", "pin-63";
> + }
> --
> 1.9.1
>
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 11/14] pinctrl: milbeaut: Add Milbeaut M10V pinctrl
2018-12-04 11:23 ` Masahiro Yamada
@ 2018-12-05 5:03 ` Sugaya, Taichi
0 siblings, 0 replies; 11+ messages in thread
From: Sugaya, Taichi @ 2018-12-05 5:03 UTC (permalink / raw)
To: Masahiro Yamada
Cc: linux-clk, DTML, linux-arm-kernel, Linux Kernel Mailing List,
linux-serial, Michael Turquette, Stephen Boyd, Rob Herring,
Mark Rutland, Greg Kroah-Hartman, Daniel Lezcano,
Thomas Gleixner, Russell King, Jiri Slaby, Masami Hiramatsu,
Jassi Brar
Hi
Thank you for your comments.
On 2018/12/04 20:23, Masahiro Yamada wrote:
> Hi Sugaya-san
>
> On Mon, Nov 19, 2018 at 10:01 AM Sugaya Taichi
> <sugaya.taichi@socionext.com> wrote:
>>
>> Add Milbeaut M10V pinctrl.
>> The M10V has the pins that can be used GPIOs or take multiple other
>> functions.
>>
>> Signed-off-by: Sugaya Taichi <sugaya.taichi@socionext.com>
>
>
> This patch was sent to:
>
> linux-clk@vger.kernel.org,
> devicetree@vger.kernel.org,
> linux-arm-kernel@lists.infradead.org,
> linux-kernel@vger.kernel.org,
> linux-serial@vger.kernel.org
>
>
>
>
> Unfortunately, the most important ML
>
> linux-gpio@vger.kernel.org
>
> was not addressed.
>
>
> The pinctrl maintainer may not notice this patch.
Ah I took a critical mistake...
>
>
>
>
>
>
>
>> diff --git a/drivers/pinctrl/pinctrl-m10v.c b/drivers/pinctrl/pinctrl-m10v.c
>> new file mode 100644
>> index 0000000..d4ca713
>> --- /dev/null
>> +++ b/drivers/pinctrl/pinctrl-m10v.c
>> @@ -0,0 +1,765 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +/*
>> + * Copyright (C) 2018 Socionext Ltd.
>> + * Copyright (C) 2015 Linaro Ltd.
>> + * Author: Jassi Brar <jaswinder.singh@linaro.org>
>
>
> My company name is "Socionext Inc." instead of "Socionext Ltd."
Yes, modify it.
>
>
>
>
>
>
>
>> +static struct platform_driver m10v_pinctrl_driver = {
>> + .probe = m10v_pinctrl_probe,
>> + .driver = {
>> + .name = "m10v-pinctrl",
>> + .of_match_table = m10v_pmatch,
>> + },
>> +};
>> +
>> +static int __init m10v_pinctrl_init(void)
>> +{
>> + return platform_driver_register(&m10v_pinctrl_driver);
>> +}
>> +arch_initcall(m10v_pinctrl_init);
>
>
> Can't it be builtin_platform_driver()?
I think using builtin_platform_driver() is no problem.
>
> Which device requires this to be arch_initcall()?
This driver was originally a module, so no need to be arch_initcall().
I will use arch_initcall() instead.
Thanks
Sugaya Taichi
>
>
>
>
>
> --
> Best Regards
> Masahiro Yamada
>
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 10/14] dt-bindings: pinctrl: milbeaut: Add Milbeaut M10V pinctrl description
2018-12-04 23:11 ` [PATCH 10/14] dt-bindings: pinctrl: milbeaut: Add Milbeaut M10V pinctrl description Rob Herring
@ 2018-12-06 8:29 ` Sugaya, Taichi
0 siblings, 0 replies; 11+ messages in thread
From: Sugaya, Taichi @ 2018-12-06 8:29 UTC (permalink / raw)
To: Rob Herring
Cc: linux-clk, devicetree, linux-arm-kernel, linux-kernel,
linux-serial, Michael Turquette, Stephen Boyd, Mark Rutland,
Greg Kroah-Hartman, Daniel Lezcano, Thomas Gleixner,
Russell King, Jiri Slaby, Masami Hiramatsu, Jassi Brar
Hi,
Thank you for your comments.
On 2018/12/05 8:11, Rob Herring wrote:
> On Mon, Nov 19, 2018 at 10:02:12AM +0900, Sugaya Taichi wrote:
>> Add DT bindings document for Milbeaut M10V pinctrl.
>>
>> Signed-off-by: Sugaya Taichi <sugaya.taichi@socionext.com>
>> ---
>> .../pinctrl/socionext,milbeaut-pinctrl.txt | 33 ++++++++++++++++++++++
>> 1 file changed, 33 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/pinctrl/socionext,milbeaut-pinctrl.txt
>>
>> diff --git a/Documentation/devicetree/bindings/pinctrl/socionext,milbeaut-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/socionext,milbeaut-pinctrl.txt
>> new file mode 100644
>> index 0000000..7469189
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/pinctrl/socionext,milbeaut-pinctrl.txt
>> @@ -0,0 +1,33 @@
>> +Milbeaut SoCs pin controller
>> +
>> +Required properties:
>> +- compatible: should be one of the following:
>> + "socionext,milbeaut-m10v-pinctrl" - for m10v SoC
>> +- reg: offset and length of the register set.
>> +- reg-names: should be "pinctrl", "exiu".
>> +- gpio-cells; should be 2.
>
> #gpio-cells
>
> gpio-controller?
Ah yes. I forgot to add it.
Add it.
>
>> +- interrupt-cells: should be 2.
>
> #interrupt-cells
>
> interrupt-controller?
Add it also.
Thanks,
Sugaya Taichi
>
>> +- clocks: phandle to the input clock.
>> +- interrupts: three interrupts specifer.
>> +- interrupt-names: corresponds "interrupts" factor.
>> +
>> +Example:
>> + pinctrl: pinctrl@1d022000 {
>> + compatible = "socionext,milbeaut-m10v-pinctrl";
>> + reg = <0x1d022000 0x1000>,
>> + <0x1c26f000 0x1000>;
>> + reg-names = "pinctrl", "exiu";
>> + gpio-controller;
>> + #gpio-cells = <2>;
>> + interrupt-controller;
>> + #interrupt-cells = <2>;
>> + clocks = <&dummy_clk>;
>> + interrupts = <0 54 4>, <0 55 4>, <0 56 4>, <0 57 4>,
>> + <0 58 4>, <0 59 4>, <0 60 4>, <0 61 4>,
>> + <0 62 4>, <0 63 4>, <0 64 4>, <0 65 4>,
>> + <0 66 4>, <0 67 4>, <0 68 4>, <0 69 4>;
>> + interrupt-names = "pin-48", "pin-49", "pin-50", "pin-51",
>> + "pin-52", "pin-53", "pin-54", "pin-55",
>> + "pin-56", "pin-57", "pin-58", "pin-59",
>> + "pin-60", "pin-61", "pin-62", "pin-63";
>> + }
>> --
>> 1.9.1
>>
^ permalink raw reply [flat|nested] 11+ messages in thread
end of thread, other threads:[~2018-12-06 8:29 UTC | newest]
Thread overview: 11+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-11-19 1:02 [PATCH 10/14] dt-bindings: pinctrl: milbeaut: Add Milbeaut M10V pinctrl description Sugaya Taichi
2018-11-19 1:02 ` [PATCH 11/14] pinctrl: milbeaut: Add Milbeaut M10V pinctrl Sugaya Taichi
2018-12-04 11:23 ` Masahiro Yamada
2018-12-05 5:03 ` Sugaya, Taichi
2018-11-19 1:02 ` [PATCH 12/14] ARM: dts: milbeaut: Add device tree set for the Milbeaut M10V board Sugaya Taichi
2018-11-19 15:46 ` Rob Herring
2018-11-21 2:36 ` sugaya.taichi
2018-11-19 1:02 ` [PATCH 13/14] ARM: configs: Add Milbeaut M10V defconfig Sugaya Taichi
2018-11-19 1:02 ` [PATCH 14/14] MAINTAINERS: Add entry to MAINTAINERS for Milbeaut Sugaya Taichi
2018-12-04 23:11 ` [PATCH 10/14] dt-bindings: pinctrl: milbeaut: Add Milbeaut M10V pinctrl description Rob Herring
2018-12-06 8:29 ` Sugaya, Taichi
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).