From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753235AbbDGIWn (ORCPT ); Tue, 7 Apr 2015 04:22:43 -0400 Received: from conssluserg004.nifty.com ([202.248.44.42]:24878 "EHLO conssluserg004-v.nifty.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1750994AbbDGIWj (ORCPT ); Tue, 7 Apr 2015 04:22:39 -0400 X-Nifty-SrcIP: [209.85.212.177] MIME-Version: 1.0 In-Reply-To: <3196164.8b31S2QWFd@wuerfel> References: <3196164.8b31S2QWFd@wuerfel> Date: Tue, 7 Apr 2015 17:22:32 +0900 Message-ID: Subject: Re: not syncing: Attempted to kill init! exitcode=0x00000004 ? From: Masahiro Yamada To: Arnd Bergmann Cc: linux-arm-kernel@lists.infradead.org, Linux Kernel Mailing List Content-Type: text/plain; charset=UTF-8 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Arnd, Thanks for your comment! 2015-04-07 16:41 GMT+09:00 Arnd Bergmann : > On Tuesday 07 April 2015 12:34:30 Masahiro Yamada wrote: >> >> What is the cause of the kernel panic? How to fix it? >> Any hint is very appreciated. >> > > Cortex-A9 usually need to set up the L2 Cache controller, and you > don't have a node for that. > > Can you try adding a DT node for it? You may also have to specify > the overrides for its aux control register in DT if that is not > set up right by the boot loader or the power-on defaults. I have not checked the L2 (outer) cache yet. The L2 cache on our SoC is not a famous IP, but our own implementation. I will have to implement L2 code as well as the device tree node. Is there any workaround to boot Linux without L2 cache? -- Best Regards Masahiro Yamada