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From: AngeloGioacchino Del Regno <kholk11@gmail.com>
To: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Andy Gross <agross@kernel.org>, Stephen Boyd <sboyd@kernel.org>,
	marijns95@gmail.com, Konrad Dybcio <konradybcio@gmail.com>,
	martin.botka1@gmail.com, MSM <linux-arm-msm@vger.kernel.org>,
	phone-devel@vger.kernel.org,
	linux-kernel <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH 3/5] clk: qcom: mmcc-sdm660: Add MDP clock source CXC to MDSS GDSC
Date: Sat, 9 Jan 2021 19:39:28 +0100	[thread overview]
Message-ID: <CAK7fi1Z0k8AE91KhjMUsBtKgu9ArEhnbfru2CYZHLDyjfgA6NQ@mail.gmail.com> (raw)
In-Reply-To: <X8sV2UOipnhP1Y78@builder.lan>

Il giorno sab 5 dic 2020 alle ore 06:08 Bjorn Andersson
<bjorn.andersson@linaro.org> ha scritto:
>
> On Sat 26 Sep 08:03 CDT 2020, kholk11@gmail.com wrote:
>
> > From: AngeloGioacchino Del Regno <kholk11@gmail.com>
> >
> > It is required for optimal performance and to avoid MDP stalls to
> > retain mem/periph on GDSC enablement: to achieve this, let's add
> > the required CXC to the MDSS GDSC.
> >
>
> Can you please explain how you came to this conclusion, I don't see the
> reference to the MDP_CLK_SRC in the downstream kernel.
>
> Thanks,
> Bjorn
>
Hey!
I am sure I don't have to go too deep with such an explanation. You know,
downstream is seriously tangled, perhaps that's why you couldn't find how.

By the way, as you can see, here in sdm660-mdss.dtsi we have the
MDP_CLK_SRC clock:
https://source.codeaurora.org/quic/la/kernel/msm-4.4/tree/arch/arm/boot/dts/qcom/sdm660-mdss.dtsi?h=LA.UM.8.2.r2-03400-sdm660.0#n121

Since downstream uses to set the mem/periph retain in a different way,
here you find
some references to what you're looking for:
https://source.codeaurora.org/quic/la/kernel/msm-4.4/tree/drivers/video/fbdev/msm/mdss_mdp.c?h=LA.UM.8.2.r2-03400-sdm660.0#n1555

...of course, also from my own tests, failing to set these flags will
stall the MDP as
soon as we hit a resume from MDP idle power collapse.

P.S.: Sorry for the late reply!
--Angelo

> > Signed-off-by: AngeloGioacchino Del Regno <kholk11@gmail.com>
> > ---
> >  drivers/clk/qcom/mmcc-sdm660.c | 2 ++
> >  1 file changed, 2 insertions(+)
> >
> > diff --git a/drivers/clk/qcom/mmcc-sdm660.c b/drivers/clk/qcom/mmcc-sdm660.c
> > index 234aca7c873b..7b1384cf8506 100644
> > --- a/drivers/clk/qcom/mmcc-sdm660.c
> > +++ b/drivers/clk/qcom/mmcc-sdm660.c
> > @@ -2572,6 +2572,8 @@ static struct gdsc mdss_gdsc = {
> >       .pd = {
> >               .name = "mdss",
> >       },
> > +     .cxcs = (unsigned int []){ 0x2040 },
> > +     .cxc_count = 1,
> >       .pwrsts = PWRSTS_OFF_ON,
> >  };
> >
> > --
> > 2.28.0
> >

  reply	other threads:[~2021-01-09 18:40 UTC|newest]

Thread overview: 21+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-09-26 13:03 [PATCH 0/5] SDM630/660 Multimedia and GPU clock controllers kholk11
2020-09-26 13:03 ` [PATCH 1/5] clk: qcom: Add SDM660 Multimedia Clock Controller (MMCC) driver kholk11
2020-09-26 13:23   ` Martin Botka
2020-09-30 20:47   ` kernel test robot
2020-10-13 14:51     ` Martin Botka
2020-10-13 15:01       ` Martin Botka
2020-12-05  4:59   ` Bjorn Andersson
2020-09-26 13:03 ` [PATCH 2/5] dt-bindings: clock: Add support for the SDM630 and SDM660 mmcc kholk11
2020-09-26 13:03 ` [PATCH 3/5] clk: qcom: mmcc-sdm660: Add MDP clock source CXC to MDSS GDSC kholk11
2020-12-05  5:08   ` Bjorn Andersson
2021-01-09 18:39     ` AngeloGioacchino Del Regno [this message]
2020-09-26 13:03 ` [PATCH 4/5] clk: qcom: Add SDM660 GPU Clock Controller (GPUCC) driver kholk11
2020-09-26 13:29   ` Martin Botka
2020-09-30 20:46   ` kernel test robot
2020-09-30 21:58     ` AngeloGioacchino Del Regno
2020-10-02  5:39       ` Philip Li
2020-12-05  5:16   ` Bjorn Andersson
2020-09-26 13:03 ` [PATCH 5/5] dt-bindings: clock: Add QCOM SDM630 and SDM660 graphics clock bindings kholk11
2020-09-26 13:30   ` Martin Botka
2020-12-05  5:14   ` Bjorn Andersson
2020-12-04 18:16 ` [PATCH 0/5] SDM630/660 Multimedia and GPU clock controllers AngeloGioacchino Del Regno

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