From: Arnd Bergmann <arnd@arndb.de>
To: Alan Kao <alankao@andestech.com>
Cc: Eric Lin <tesheng@andestech.com>, Gary Guo <gary@garyguo.net>,
alex@ghiti.fr,
David Abdurachmanov <david.abdurachmanov@gmail.com>,
Anup Patel <Anup.Patel@wdc.com>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
Andrew Morton <akpm@linux-foundation.org>,
Steven Price <steven.price@arm.com>,
atish.patra@wdc.com, yash.shah@sifive.com,
Albert Ou <aou@eecs.berkeley.edu>,
Palmer Dabbelt <palmer@dabbelt.com>,
Greentime Hu <green.hu@gmail.com>,
zong.li@sifive.com, Paul Walmsley <paul.walmsley@sifive.com>,
Mike Rapoport <rppt@linux.ibm.com>,
Thomas Gleixner <tglx@linutronix.de>,
Borislav Petkov <bp@suse.de>,
Logan Gunthorpe <logang@deltatee.com>,
linux-riscv@lists.infradead.org
Subject: Re: [PATCH 0/3] Highmem support for 32-bit RISC-V
Date: Wed, 8 Apr 2020 16:40:17 +0200 [thread overview]
Message-ID: <CAK8P3a1JS3_2fWrhNTZx0eTWjJa-GTb4AscTPqydpSP5EB15Yw@mail.gmail.com> (raw)
In-Reply-To: <20200408035118.GA1451@andestech.com>
On Wed, Apr 8, 2020 at 5:52 AM Alan Kao <alankao@andestech.com> wrote:
> On Thu, Apr 02, 2020 at 11:31:37AM +0200, Arnd Bergmann wrote:
> > On Tue, Mar 31, 2020 at 11:34 AM Eric Lin <tesheng@andestech.com> wrote:
> > For the arm32 architecture, we are thinking about implementing a
> > VMPLIT_4G_4G option to replace highmem in the long run. The most
> > likely way this would turn out at the moment looks like:
> >
>
> Thanks for sharing the status from ARM32. Is there any available branch
> already? It would be good to have a reference implementation.
No code yet, so far not much more than the ideas that I listed. We
are currently looking for someone interested in doing the work
or maybe sponsoring it if they have a strong interest.
If someone does it for RISC-V first, that would of course also help on ARM ;-)
> > - have a 256MB region for vmalloc space at the top of the 4GB address
> > space, containing vmlinux, module, mmio mappings and vmalloc
> > allocations
> >
> > - have 3.75GB starting at address zero for either user space or the
> > linear map.
> >
> > - reserve one address space ID for kernel mappings to avoid tlb flushes
> > during normal context switches
> >
> > - On any kernel entry, switch the page table to the one with the linear
> > mapping, and back to the user page table before returning to user space
> >
>
> After some survey I found previous disccusion
> (https://lkml.org/lkml/2019/4/24/2110). The 5.2-based patch ended up not
> being merged. But at least we will have something to start if we want to.
Ah, I see. What is the current requirement for ASIDs in hardware
implementations? If support for more than one address space is
optional, that would make the VMSPLIT_4G support fairly expensive
as it requires a full TLB flush for each context switch.
> Also interestingly, there was a PR for privileged spec that separates
> addressing modes (https://github.com/riscv/riscv-isa-manual/pull/128) as
> Sdas extension, but there was no progress afterwards.
Right, this sounds like the ideal implementation. This is what is done
in arch/s390 and probably a few of the others.
> Not very related to this thread, but there were some discussion about
> ASID design in RISC-V (https://github.com/riscv/riscv-isa-manual/issues/348).
> It is now in ratified 1.11 privileged spec.
Ok, so I suppose that would apply to about half the 32-bit implementations
and most of the future ones, but not the ones implementing the 1.10 spec
or earlier, right?
> It seems to me that VMSPLIT_4G_4G is quite different from other VMSPLITs,
> because it requires much more changes.
>
> Thanks for showing the stance of kernel community against HIGHMEM support.
> The cited discussion thread is comprehensive and clear. Despite that RV32
> users cannot get upstream support for their large memory, mechnisms like
> VMSPLIT_4G_4G seems to be a promising way to go. That being said, to
> support the theoretical 16G physical memory, eventually kmap* will still
> be needed.
I had not realized that Sv32 supports more than 4GB physical address
space at all. I agree that if someone puts that much RAM into a machine,
there are few alternatives to highmem (in theory one could use the
extra RAM for zswap/zram, but that's not a good replacement).
OTOH actually using more than 1GB or 2GB of physical memory on a
32-bit core is something that I expect to become completely obscure
in the future, as this is where using 32-bit cores tends to get
uneconomical. The situation that I observe across the currently supported
32-bit architectures in the kernel is that:
- There is an incentive to run 32-bit on machines with 1GB of RAM or less
if you have the choice, because of higher memory consumption and
cache utilization on 64-bit code. On systems with 2GB or more, the
cost of managing that memory using 32-bit code usually outweighs
the benefits and you should run at least a 64-bit kernel.
- The high end 32-bit cores (Arm Cortex-A15/A17, MIPS P5600,
PowerPC 750, Intel Pentium 4, Andes A15/D15, ...) are all obsolete
after the follow-on products use 64-bit cores on a smaller process
node, which end up being more capable, faster *and* cheaper.
- The 32-bit cores that do survive are based on simpler in-order
pipelines that are cheaper and can still beat the 64-bit cores in
terms of cost (mostly chip area, sometimes royalties), but not
performance. This includes Arm Cortex-A7, MIPS 24k and typical
RV32 cores.
- On an SoC with a cheap and simple CPU core, there is no point
in spending a lot of money/area/complexity on a high-end memory
controller. On single-core 32-bit SoCs, you usually end up with single
16 or 32-bit wide DDR2 memory controller, on an SMP system like
most quad-Cortex-A7, you have a 32-bit wide DDR3 controller, but no
DDR4 or LP-DDR3/4.
- The largest economical memory configuration on a 32-bit DDR3
controller is to have two 256Mx16 chips for a total of 1GB. You can
get 2GB with four chips using dual-channel controllers or 512Mx8
memory, but anything beyond that is much more expensive than
upgrading to a 64-bit SoC with LP-DDR4.
This is unlikely to change over time as 64-bit chips are also getting
cheaper and may replace more of the 32-bit chips we see today.
In particular, I expect to see multi-core chips moving to mostly
64-bit cores over time, while 32-bit chips keep using one or
occasionally two cores, further reducing the need for large and/or
fast memory.
Arnd
next prev parent reply other threads:[~2020-04-08 14:40 UTC|newest]
Thread overview: 44+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-03-31 9:32 [PATCH 0/3] Highmem support for 32-bit RISC-V Eric Lin
2020-03-31 9:32 ` [PATCH 1/3] riscv/mm: Add pkmap region and CONFIG_HIGHMEM Eric Lin
2020-03-31 9:32 ` [PATCH 2/3] riscv/mm: Implement kmap() and kmap_atomic() Eric Lin
2020-03-31 9:32 ` [PATCH 3/3] riscv/mm: Add pkmap in print_vm_layout() Eric Lin
2020-04-02 9:31 ` [PATCH 0/3] Highmem support for 32-bit RISC-V Arnd Bergmann
2020-04-08 3:51 ` Alan Kao
2020-04-08 14:40 ` Arnd Bergmann [this message]
2020-04-14 15:17 ` afzal mohammed
2020-04-14 19:29 ` Arnd Bergmann
2020-04-15 13:54 ` afzal mohammed
2020-05-03 14:50 ` afzal mohammed
2020-05-03 20:20 ` Arnd Bergmann
2020-05-04 9:10 ` afzal mohammed
2020-05-04 11:27 ` Arnd Bergmann
2020-05-11 14:21 ` ARM: static kernel in vmalloc space (was Re: [PATCH 0/3] Highmem support for 32-bit RISC-V) afzal mohammed
2020-05-11 15:29 ` Arnd Bergmann
2020-05-12 10:47 ` ARM: static kernel in vmalloc space afzal mohammed
2020-05-12 19:49 ` Arnd Bergmann
2020-05-14 11:17 ` afzal mohammed
2020-05-14 12:41 ` Arnd Bergmann
2020-05-14 13:35 ` afzal mohammed
2020-05-14 14:44 ` afzal mohammed
2020-05-14 15:32 ` Arnd Bergmann
2020-05-16 6:06 ` afzal mohammed
2020-05-16 7:35 ` Arnd Bergmann
2020-06-07 12:59 ` ARM: vmsplit 4g/4g afzal mohammed
2020-06-07 16:11 ` Russell King - ARM Linux admin
2020-06-08 11:09 ` afzal mohammed
2020-06-10 10:10 ` Linus Walleij
2020-06-12 10:25 ` afzal mohammed
2020-06-15 9:11 ` Linus Walleij
2020-06-15 10:01 ` afzal mohammed
2020-06-07 19:26 ` Arnd Bergmann
2020-06-08 11:18 ` afzal mohammed
2020-06-08 14:43 ` Arnd Bergmann
2020-06-08 15:17 ` afzal mohammed
2020-06-09 12:15 ` afzal mohammed
2020-06-09 14:22 ` Arnd Bergmann
2020-05-14 16:25 ` ARM: static kernel in vmalloc space Russell King - ARM Linux admin
2020-05-14 21:12 ` Arnd Bergmann
2020-05-14 23:40 ` Russell King - ARM Linux admin
2020-05-15 15:41 ` Arnd Bergmann
2020-07-30 9:33 ` Linus Walleij
2020-07-30 10:17 ` Arnd Bergmann
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