From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.2 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id AA181C433DB for ; Tue, 12 Jan 2021 13:56:29 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 7690422B30 for ; Tue, 12 Jan 2021 13:56:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729782AbhALN4B (ORCPT ); Tue, 12 Jan 2021 08:56:01 -0500 Received: from mail.kernel.org ([198.145.29.99]:45814 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726184AbhALN4A (ORCPT ); Tue, 12 Jan 2021 08:56:00 -0500 Received: by mail.kernel.org (Postfix) with ESMTPSA id 4EA9523125; Tue, 12 Jan 2021 13:55:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1610459719; bh=JtgDus3RlRKCNLMJU5n8LTJwheyPVPV3P1FCNE/3hDQ=; h=References:In-Reply-To:From:Date:Subject:To:Cc:From; b=UUHNrIoGgg39yGyWAmKBqQE3T7Nc2vpJdJBqK8PNMSXEC/xPTRzwN+q83W5WmsvJm ln71BYNMEsnE6Aim3WTmcVwKzctUfdolP5Rqd+9/3naBgHTyHhyOgb+mqxg+6zd7Cs l/vGKpCWAaRXoJHA2a2DqsdRxowq2yCYTiuJdVAxh1R6AfxkdNBJTQmX54HFH10bay NciPc0Sokd/GAfj9nIUG8jnMwkeqnFRUgpiEckP74+GRCvYfkeGTLqlCkW01kvD4qN 6Bl7nz9Gc/eYPI72KeZk6mzYxH6IK8TFVU+tSg3xN2IX0Mk+HLc8Jrl3skKJcjZVh4 MJzFKRHLHqmoQ== Received: by mail-ot1-f54.google.com with SMTP id j20so2302257otq.5; Tue, 12 Jan 2021 05:55:19 -0800 (PST) X-Gm-Message-State: AOAM532pvUPDbTcCmM3S70cMUinyCzMCGJhswaGvm6m/LueQWEyDGBRu Ku62uUqEZovcoDOmTrnHGXxrXekQZejvIJ6ZZuk= X-Google-Smtp-Source: ABdhPJyjfW3VIxHOGv1CcXu0RcKWWw84/dtZP4ZYXG4Ahn9W5rp0DQ0WHXCtgyU0xjgg5DHlYP5JPWYtXgwzRqdK8IE= X-Received: by 2002:a9d:7a4b:: with SMTP id z11mr2830989otm.305.1610459718264; Tue, 12 Jan 2021 05:55:18 -0800 (PST) MIME-Version: 1.0 References: <20210112015602.497-1-thunder.leizhen@huawei.com> <20210112015602.497-3-thunder.leizhen@huawei.com> In-Reply-To: From: Arnd Bergmann Date: Tue, 12 Jan 2021 14:55:02 +0100 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v3 2/3] dt-bindings: arm: hisilicon: Add binding for L3 cache controller To: "Leizhen (ThunderTown)" Cc: Russell King , Greg Kroah-Hartman , Will Deacon , Haojian Zhuang , Arnd Bergmann , Rob Herring , Wei Xu , devicetree , linux-arm-kernel , linux-kernel Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Jan 12, 2021 at 1:35 PM Leizhen (ThunderTown) wrote: > On 2021/1/12 16:46, Arnd Bergmann wrote: > > On Tue, Jan 12, 2021 at 2:56 AM Zhen Lei wrote: > > > >> +--- > >> +$id: http://devicetree.org/schemas/arm/hisilicon/l3cache.yaml# > >> +$schema: http://devicetree.org/meta-schemas/core.yaml# > >> + > >> +title: Hisilicon L3 cache controller > >> + > >> +maintainers: > >> + - Wei Xu > >> + > >> +description: | > >> + The Hisilicon L3 outer cache controller supports a maximum of 36-bit physical > >> + addresses. The data cached in the L3 outer cache can be operated based on the > >> + physical address range or the entire cache. > >> + > >> +properties: > >> + compatible: > >> + items: > >> + - const: hisilicon,l3cache > >> + > > > > The compatible string needs to be a little more specific, I'm sure > > you cannot guarantee that this is the only L3 cache controller ever > > designed in the past or future by HiSilicon. > > > > Normally when you have an IP block that is itself unnamed but that is specific > > to one or a few SoCs but that has no na, the convention is to include the name > > of the first SoC that contained it. > > Right, thanks for your suggestion, I will rename it to "hisilicon,hi1381-l3cache" > and "hisilicon,hi1215-l3cache". Sounds good. > > Can you share which products actually use this L3 cache controller? > > This L3 cache controller is used on Hi1381 and Hi1215 board. I don't know where > these two boards are used. Our company is too large. Software is delivered level > by level. I'm only involved in the Kernel-related part. > > > > > On a related note, what does the memory map look like on this chip? > > memory@a00000 { > device_type = "memory"; > reg = <0x0 0xa00000 0x0 0x1aa00000>, <0x1 0xe0000000 0x0 0x1d000000>, <0x0 0x1f400000 0x0 0xb5c00000>; > }; > > Currently, the DTS is being maintained by ourselves, I'll try to upstream it later. > > > Do you support more than 4GB of total installed memory? If you > > Currently, the total size does not exceed 4 GB. However, the physical address is wider than 32 bits. Ok, so it appears that the memory is actually contiguous in the first 3.5GB (with a few holes), plus the remaining 0.5GB being offset in the physical memory by 4GB (starting at 0x1e0000000 instead of 0xe0000000), presumably to allow the use of 32-bit DMA addresses. This works fine for the moment, but it does require support for a nonlinear virt_to_phys()/phys_to_virt() translation after highmem gets removed, and you would get at most 3.75GB anyway, so it might be easier at that point to just drop the entire last block at 0x1e0000000, but this will depend on how well we get the 4G:4G code to work, and whether the users will still need kernel updates for this platform then. Arnd