From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 805F1C388F7 for ; Tue, 10 Nov 2020 20:38:21 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id E82122064B for ; Tue, 10 Nov 2020 20:38:20 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=kernel.org header.i=@kernel.org header.b="ydR4/Eir" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731407AbgKJUiU (ORCPT ); Tue, 10 Nov 2020 15:38:20 -0500 Received: from mail.kernel.org ([198.145.29.99]:53892 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727275AbgKJUiT (ORCPT ); Tue, 10 Nov 2020 15:38:19 -0500 Received: from mail-ot1-f50.google.com (mail-ot1-f50.google.com [209.85.210.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 6A4452063A for ; Tue, 10 Nov 2020 20:38:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1605040698; bh=dC2cst0+NehiX2IqKyhIGqMDMr6AVk93A52+2YUUDYA=; h=References:In-Reply-To:From:Date:Subject:To:Cc:From; b=ydR4/EiraONC/eDzv3t+v7EPeyfeQc1mmt2M/m+lKadnm8O1QU9H71rzaLzkKUiN8 zYyCdDCpN8vphm6svn66M1VfMUesY8cq2Fb7w8puJlZg6lEpH/BuH+pHwMosQ9/MxZ V72En7fsMYWUBX52drVvNfBuPlUjB6Obe4auUmho= Received: by mail-ot1-f50.google.com with SMTP id l36so6136ota.4 for ; Tue, 10 Nov 2020 12:38:18 -0800 (PST) X-Gm-Message-State: AOAM5318EezkBzgoA/tfEJagFmn2AIHRAK/hYpkB0ULRB2fSDaTz2kkg DHYWzlDQNDRfnDRZZwBrBMG3L4FZRbBM7GsLFsU= X-Google-Smtp-Source: ABdhPJxWsltJYzyOIUKf+sHvuw0kAUSXKj+mqDZv0jEhae06t2cIBzZfqPoE0IenaIXO6cMdDs5B/+1apE8QpJAq2GQ= X-Received: by 2002:a05:6830:22d2:: with SMTP id q18mr13918918otc.305.1605040697642; Tue, 10 Nov 2020 12:38:17 -0800 (PST) MIME-Version: 1.0 References: <20200409232728.231527-1-caij2003@gmail.com> <20201107001056.225807-1-jiancai@google.com> In-Reply-To: From: Arnd Bergmann Date: Tue, 10 Nov 2020 21:38:01 +0100 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v2] Make iwmmxt.S support Clang's integrated assembler To: Nick Desaulniers Cc: Jian Cai , Ard Biesheuvel , Manoj Gupta , Luis Lozano , clang-built-linux , Russell King , Nathan Chancellor , Linux ARM , Linux Kernel Mailing List Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Nov 10, 2020 at 9:11 PM 'Nick Desaulniers' via Clang Built Linux wrote: > > On Tue, Nov 10, 2020 at 12:10 PM Jian Cai wrote: > > > > I tried to verify with ixp4xx_defconfig, and I noticed it also used CONFIG_CPU_BIG_ENDIAN=y to enable big endianness as follows, > > > > linux$ grep ENDIAN arch/arm/configs/ixp4xx_defconfig > > CONFIG_CPU_BIG_ENDIAN=y > > > > Also it appeared arch/arm/kernel/iwmmxt.o was not built with ixp4xx_defconfig. The commands I used > > > > linux$ARCH=arm CROSS_COMPILE=arm-linux-gnueabihf- make CC=clang ixp4xx_defconfig > > linux$ARCH=arm CROSS_COMPILE=arm-linux-gnueabihf- make -j32 CC=clang > > linux$ ls arch/arm/kernel/iwmmxt.o > > ls: cannot access 'arch/arm/kernel/iwmmxt.o': No such file or directory > > > > Did I miss any steps? > > Yes, you need to manually enable CONFIG_IWMMXT in menuconfig or via > `scripts/configs -e`. To clarify: ixp4xx and pxa3xx were two platforms based on the XScale core. ixp4xx was commonly used in big-endian mode but lacked iWMMXt. pxa3xx had iWMMXt but doesn't allow enabling big-endian mode because of a Kconfig dependency, meaning that nobody has ever tried it, and it's likely broken. Later 'mvebu' parts (Armada 510) do have iWMMXt and allow big-endian mode, but those are BE8, with non-reversed byteorder for the instructions. So none of this matters in practice, but it's very satifiying to know it is finally all working with the integrated assembler in all those combinations, at least in theory! Arnd