From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.5 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DE004C43214 for ; Mon, 23 Aug 2021 01:06:07 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C526B61037 for ; Mon, 23 Aug 2021 01:06:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234492AbhHWBGs (ORCPT ); Sun, 22 Aug 2021 21:06:48 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44546 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233963AbhHWBGq (ORCPT ); Sun, 22 Aug 2021 21:06:46 -0400 Received: from mail-ej1-x632.google.com (mail-ej1-x632.google.com [IPv6:2a00:1450:4864:20::632]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1366FC061760 for ; Sun, 22 Aug 2021 18:06:05 -0700 (PDT) Received: by mail-ej1-x632.google.com with SMTP id me10so5051451ejb.11 for ; Sun, 22 Aug 2021 18:06:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=pensando.io; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=DiGtvvH8NkIVd4hqCUiszMleyUhfYfWw1b6ZDZbLUkE=; b=uhWvv9wnJvdEuINozK+RdVuTibj+UvYVWqnvk3DidpO+D6vtOAXbizZtIoU+1RzTmr neD6qgJ86ggq3V1tinDW/48juLqA91oBDkn/NB65JOJLHe8ghFOwkQ1zgaxlQMH9WODi rt9SNazJrbwjf3VFwt6U5hKEGhpmSs7w4dXX8sSJt472vdiwC3vAF5s/p3iinYjxtwBl a9cj3j653TZKo2jXSHjebMJ7KoKkwr3MDOz9cwalouCmaCPDQmETbtb4GGf4v7OOCExP B2zmwqQPZYp77TN2JzvGf7JzCIuJYxdNvTcTfjBdZOlLi5LS1YiO9oc0f/v1VUpM86FM Bj+w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=DiGtvvH8NkIVd4hqCUiszMleyUhfYfWw1b6ZDZbLUkE=; b=JbIPfZzGjXw/3fAupnWq+lKQqg4P3180JKW7q1rt4+CP8RuC3evwZndHYFQAaM4+PO 3d1l/zIKSGBVuas8ay54MMpBNzeen1JydXu79Y44Fyazve4PC6Yu+We5P024dvkkvMpq w3UAJkpyUwTPpx+unHm+Y4aJE0ofnBWeWZT43hkE/vu1GzzzVej5ppvtfWN7rDdmeIz2 YRscHcu+lG18fYWhb1wdRLcv8lurxpyzg229dd0LIHzMOEyVMwAW1/Y2/sCyNBtv7lKB 5m3h9QzU2jSW4zYLm7+YkSrN6Rz5iLaM1KTqRWF4KgJdDoC2xNUtMS8Dj+XS4eJ18WzV Eyiw== X-Gm-Message-State: AOAM530Jm2qBdQzKyv3QAdtGewyTxFUXQqBw681OGXjoR2lKeyqSIpKn PUmPOHBv1po+gph81OxEMiUpXjrFv8OTw7oagAFc8A== X-Google-Smtp-Source: ABdhPJw9eEJEPtVIYbe2803vRNA11NSXlz157yzpl7w09FqgV8tkGsFwFNzMcmgt5u7Zt114aJklS9Z5BHq/3A2TpJA= X-Received: by 2002:a17:906:2f15:: with SMTP id v21mr21088372eji.444.1629680763004; Sun, 22 Aug 2021 18:06:03 -0700 (PDT) MIME-Version: 1.0 References: <20210304034141.7062-1-brad@pensando.io> <20210304034141.7062-2-brad@pensando.io> <20210304091025.ny52qjm7wbfvmjgl@mobilestation> In-Reply-To: From: Brad Larson Date: Sun, 22 Aug 2021 18:05:52 -0700 Message-ID: Subject: Re: [PATCH 1/8] gpio: Add Elba SoC gpio driver for spi cs control To: Linus Walleij Cc: Serge Semin , Linux ARM , Arnd Bergmann , Bartosz Golaszewski , Mark Brown , Adrian Hunter , Ulf Hansson , Olof Johansson , "open list:GPIO SUBSYSTEM" , linux-spi , linux-mmc , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , "linux-kernel@vger.kernel.org" Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Linus, On Thu, Mar 4, 2021 at 5:38 AM Linus Walleij wrote: > > On Thu, Mar 4, 2021 at 10:10 AM Serge Semin wrote: > > On Thu, Mar 04, 2021 at 09:29:33AM +0100, Linus Walleij wrote: > > > > > + * pin: 3 2 | 1 0 > > > > + * bit: 7------6------5------4----|---3------2------1------0 > > > > + * cs1 cs1_ovr cs0 cs0_ovr | cs1 cs1_ovr cs0 cs0_ovr > > > > + * ssi1 | ssi0 > > > > + */ > > > > +#define SPICS_PIN_SHIFT(pin) (2 * (pin)) > > > > +#define SPICS_MASK(pin) (0x3 << SPICS_PIN_SHIFT(pin)) > > > > +#define SPICS_SET(pin, val) ((((val) << 1) | 0x1) << SPICS_PIN_SHIFT(pin)) > > > > > > > > So 2 bits per GPIO line in one register? (Nice doc!) > > > > I suppose the first bit is the CS-pin-override flag. So when it's set > > the output is directly driven by the second bit, otherwise the > > corresponding DW APB SPI controller drives it. That's how the > > multiplexing is implemented here. > > If these output lines are so tightly coupled to the SPI block > and will not be used for any other GPO (general purpose output) > I think it makes more sense to bundle the handling into the > DW SPI driver, and activate it based on the Elba compatible > string (if of_is_compatible(...)). > > I am a bit cautious because it has happened in the past that > people repurpose CS lines who were originally for SPI CS > to all kind of other purposes, such as a power-on LED and > in that case it needs to be a separate GPIO driver. So the > author needs to have a good idea about what is a realistic > use case here. The gpio pins being used for the Elba SoC SPI CS are dedicated to this function. Are you recommending that the code in drivers/gpio/gpio-elba-spics.c be integrated into drivers/spi/spi-dw-mmio.c? Regards, Brad