From: Avi Fishman <avifishman70@gmail.com>
To: Tomer Maimon <tmaimon77@gmail.com>,
Tali Perry <tali.perry1@gmail.com>,
Patrick Venture <venture@google.com>,
Nancy Yuen <yuenn@google.com>,
Benjamin Fair <benjaminfair@google.com>,
Daniel Lezcano <daniel.lezcano@linaro.org>,
Thomas Gleixner <tglx@linutronix.de>,
Avi Fishman <avifishman70@gmail.com>
Cc: OpenBMC Maillist <openbmc@lists.ozlabs.org>,
Linux Kernel Mailing List <linux-kernel@vger.kernel.org>
Subject: [PATCH] [v2] clocksource/drivers/npcm: fix GENMASK and timer operation
Date: Mon, 15 Jul 2019 18:19:54 +0300 [thread overview]
Message-ID: <CAKKbWA5nwsa5kcZ8GCuC3WKJptb6RtZ65izFphd=KaALqeg+BA@mail.gmail.com> (raw)
In-Reply-To: <CAKKbWA6S7KotAFtLO=ow=XYnLL2Ny5Mz2kcgM1cs+j=5mHQNmw@mail.gmail.com>
clocksource/drivers/npcm: fix GENMASK and timer operation
NPCM7XX_Tx_OPER GENMASK() changed from (27, 3) to (28, 27)
in npcm7xx_timer_oneshot() the original NPCM7XX_REG_TCSR0 register was
read again after masking it with ~NPCM7XX_Tx_OPER so the masking didn't
take effect.
npcm7xx_timer_periodic() was not wrong but it wrote to NPCM7XX_REG_TICR0
in a middle of read modify write to NPCM7XX_REG_TCSR0 which is
confusing.
Signed-off-by: Avi Fishman <avifishman70@gmail.com>
---
drivers/clocksource/timer-npcm7xx.c | 9 +++------
1 file changed, 3 insertions(+), 6 deletions(-)
diff --git a/drivers/clocksource/timer-npcm7xx.c
b/drivers/clocksource/timer-npcm7xx.c
index 8a30da7f083b..9780ffd8010e 100644
--- a/drivers/clocksource/timer-npcm7xx.c
+++ b/drivers/clocksource/timer-npcm7xx.c
@@ -32,7 +32,7 @@
#define NPCM7XX_Tx_INTEN BIT(29)
#define NPCM7XX_Tx_COUNTEN BIT(30)
#define NPCM7XX_Tx_ONESHOT 0x0
-#define NPCM7XX_Tx_OPER GENMASK(27, 3)
+#define NPCM7XX_Tx_OPER GENMASK(28, 27)
#define NPCM7XX_Tx_MIN_PRESCALE 0x1
#define NPCM7XX_Tx_TDR_MASK_BITS 24
#define NPCM7XX_Tx_MAX_CNT 0xFFFFFF
@@ -84,8 +84,6 @@ static int npcm7xx_timer_oneshot(struct
clock_event_device *evt)
val = readl(timer_of_base(to) + NPCM7XX_REG_TCSR0);
val &= ~NPCM7XX_Tx_OPER;
-
- val = readl(timer_of_base(to) + NPCM7XX_REG_TCSR0);
val |= NPCM7XX_START_ONESHOT_Tx;
writel(val, timer_of_base(to) + NPCM7XX_REG_TCSR0);
@@ -97,12 +95,11 @@ static int npcm7xx_timer_periodic(struct
clock_event_device *evt)
struct timer_of *to = to_timer_of(evt);
u32 val;
+ writel(timer_of_period(to), timer_of_base(to) + NPCM7XX_REG_TICR0);
+
val = readl(timer_of_base(to) + NPCM7XX_REG_TCSR0);
val &= ~NPCM7XX_Tx_OPER;
-
- writel(timer_of_period(to), timer_of_base(to) + NPCM7XX_REG_TICR0);
val |= NPCM7XX_START_PERIODIC_Tx;
-
writel(val, timer_of_base(to) + NPCM7XX_REG_TCSR0);
return 0;
--
2.18.0
next prev parent reply other threads:[~2019-07-15 15:20 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-07-15 10:05 [PATCH] clocksource/drivers/npcm: fix GENMASK and timer operation Avi Fishman
2019-07-15 12:37 ` Thomas Gleixner
2019-07-15 15:01 ` Avi Fishman
2019-07-15 15:08 ` Thomas Gleixner
2019-07-15 15:19 ` Avi Fishman [this message]
2019-07-15 15:25 ` [PATCH] [v2] " Joe Perches
2019-07-15 15:48 ` Avi Fishman
2019-07-15 15:42 ` [PATCH] [v3] " Avi Fishman
2019-07-22 9:15 ` Thomas Gleixner
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