From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.9 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 85D16C433E7 for ; Thu, 15 Oct 2020 08:22:53 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 212362224A for ; Thu, 15 Oct 2020 08:22:53 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ffwll.ch header.i=@ffwll.ch header.b="T9t6g+yo" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388163AbgJOIWw (ORCPT ); Thu, 15 Oct 2020 04:22:52 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56764 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730192AbgJOIWv (ORCPT ); Thu, 15 Oct 2020 04:22:51 -0400 Received: from mail-ot1-x342.google.com (mail-ot1-x342.google.com [IPv6:2607:f8b0:4864:20::342]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5CF44C0613D2 for ; Thu, 15 Oct 2020 01:22:51 -0700 (PDT) Received: by mail-ot1-x342.google.com with SMTP id f37so2125418otf.12 for ; Thu, 15 Oct 2020 01:22:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ffwll.ch; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=RbfF8nokdxqbUPmfp9WHmzX//GvXPuhhpFjfx5IA4wQ=; b=T9t6g+yo9ymX56V38aolG1A/9KAXyZikIasm30R3Ko9pDE6EYmLbKUHzK5HXSbKBO5 qbeM9yPK6Oz+xJGZMEgWEmIggYkYMU2WT+lQRC32PoOW9lfmZBB0rJTUStrIGRbZDE7u 0WYfEqGYRzSUsx63jezpHV/KBj26eNgLxMvbQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=RbfF8nokdxqbUPmfp9WHmzX//GvXPuhhpFjfx5IA4wQ=; b=dpOud6efQ9f7BkRNjFQqV9doYrg0Y7b7TBpHf7eV3ZUKI7KlKw6DggzssbvNUXEYTK 72Dm6GOADDrT6L0Vr3Y1tXXcbPHSBKOyh5uZC0yHvwZ5ejgyS8JhiptbQ2qHoZIPC1RG zg6zwrH9QFXvphtb3hN21+NxxPb6m+lkqGlV0TUG0d1Rv1uqG7VxUHhK/iEvSXxcjFIv jC+tQe8ZN7VPnfPuZG2hyYYi4sj+jqm26/FL+VIyV6o8dcNp8YvJLs+EGImXsJe+12tw 4QiMOZeh52gGduw1fvAEdJZUypdD91ZgaZ05xxS1YC3e0cc0hB2pKcx9HI000l4jLNYS z5NA== X-Gm-Message-State: AOAM530Z+J55M26UAKvCxzjO8NuSAheLFapC1mk+O53E6ni7RX+2Ekfj olez3N5L25/BaGif3BTN7LXvoExH8EHThJgiQ7nxYL+k4JNp0g== X-Google-Smtp-Source: ABdhPJxXDNGfotqx0v5QajM2+CxwSI2ZMgsiK/moGuNgteF9MFJDikzgLrlsfcADZyubWdUn1wBehOQaLWfNouKU5kI= X-Received: by 2002:a05:6830:8b:: with SMTP id a11mr1814721oto.303.1602750170682; Thu, 15 Oct 2020 01:22:50 -0700 (PDT) MIME-Version: 1.0 References: <20201012020958.229288-1-robdclark@gmail.com> <20201012020958.229288-23-robdclark@gmail.com> <20201012144018.GB438822@phenom.ffwll.local> <20201013110826.GD438822@phenom.ffwll.local> In-Reply-To: From: Daniel Vetter Date: Thu, 15 Oct 2020 10:22:39 +0200 Message-ID: Subject: Re: [Freedreno] [PATCH v2 22/22] drm/msm: Don't implicit-sync if only a single ring To: Rob Clark Cc: dri-devel , Rob Clark , Sean Paul , David Airlie , "open list:DRM DRIVER FOR MSM ADRENO GPU" , "open list:DRM DRIVER FOR MSM ADRENO GPU" , open list Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Oct 13, 2020 at 6:15 PM Rob Clark wrote: > > On Tue, Oct 13, 2020 at 4:08 AM Daniel Vetter wrote: > > > > On Mon, Oct 12, 2020 at 08:07:38AM -0700, Rob Clark wrote: > > > On Mon, Oct 12, 2020 at 7:40 AM Daniel Vetter wrote: > > > > > > > > On Sun, Oct 11, 2020 at 07:09:49PM -0700, Rob Clark wrote: > > > > > From: Rob Clark > > > > > > > > > > Any cross-device sync use-cases *must* use explicit sync. And if there > > > > > is only a single ring (no-preemption), everything is FIFO order and > > > > > there is no need to implicit-sync. > > > > > > > > > > Mesa should probably just always use MSM_SUBMIT_NO_IMPLICIT, as behavior > > > > > is undefined when fences are not used to synchronize buffer usage across > > > > > contexts (which is the only case where multiple different priority rings > > > > > could come into play). > > > > > > > > Uh does this mean msm is broken on dri2/3 and wayland? Or I'm I just > > > > confused by your commit message? > > > > > > No, I don't think so. If there is only a single priority level > > > ringbuffer (ie. no preemption to higher priority ring) then everything > > > is inherently FIFO order. > > > > Well eventually you get a scheduler I guess/hope :-) > > we do have one currently for some gens, but not others.. hence the > check for # of rings. (Ie. there is a ring per priority level, if > only one ring, that means no preemption/scheduler) Even without preempt a scheduler is somewhat useful, if you have a very spammy client. Of course it assumes that everyone submits reasonably short workloads, otherwise nothing you can do. > > > For cases where we are sharing buffers with something external to drm, > > > explicit sync will be used. And we don't implicit sync with display, > > > otherwise x11 (frontbuffer rendering) would not work > > > > Uh now I'm even more confused. The implicit sync fences in dma_resv are > > kinda for everyone. That's also why dma_resv with the common locking > > approach is a useful idea. > > > > So display should definitely support implicit sync, and iirc msm does have > > the helper hooked up. > > yup > > > Wrt other subsystems, I guess passing dma_fence around somehow doesn't fit > > into v4l (the patches never landed), so v4l doesn't do any kind of sync > > right now. But this could be fixed. Not sure what else is going on. > > > > So I guess I still have no idea why you put that into the commit message. > > > > btw for what you're trying to do yourself, the way to do this is to > > allocate a fence timeline for your engine, compare fences, and no-op them > > all out if their own the same timeline. > > we do that already (with a fence timeline per-ring, in the case of > gens which support multiple rings / preemption).. this patch just > short-circuits that in the case where we already knows the fences will > of the same timeline Ok so I think it's all good, no misunderstanding, but the commit message. I think if you delete the first sentence that cross-device sync must use explicit fences then it all makes sense and is consistent. Or clarify it that this is cross-engine sync with explicit internal synchronization, to differentiate it against cross-device sync (as seen by userspace, like different drm_device instances) and explicit dma_fence synchronization controlled by userspace. -Daniel > BR, > -R > > > -Daniel > > > > > > > > BR, > > > -R > > > > > > > Since for these protocols we do expect implicit sync accross processes to > > > > work. Even across devices (and nvidia have actually provided quite a bunch > > > > of patches to make this work in i915 - ttm based drivers get this right, > > > > plus dumb scanout drivers using the right helpers also get this all > > > > right). > > > > -Daniel > > > > > > > > > > > > > > Signed-off-by: Rob Clark > > > > > --- > > > > > drivers/gpu/drm/msm/msm_gem_submit.c | 7 ++++--- > > > > > 1 file changed, 4 insertions(+), 3 deletions(-) > > > > > > > > > > diff --git a/drivers/gpu/drm/msm/msm_gem_submit.c b/drivers/gpu/drm/msm/msm_gem_submit.c > > > > > index 3151a0ca8904..c69803ea53c8 100644 > > > > > --- a/drivers/gpu/drm/msm/msm_gem_submit.c > > > > > +++ b/drivers/gpu/drm/msm/msm_gem_submit.c > > > > > @@ -277,7 +277,7 @@ static int submit_lock_objects(struct msm_gem_submit *submit) > > > > > return ret; > > > > > } > > > > > > > > > > -static int submit_fence_sync(struct msm_gem_submit *submit, bool no_implicit) > > > > > +static int submit_fence_sync(struct msm_gem_submit *submit, bool implicit_sync) > > > > > { > > > > > int i, ret = 0; > > > > > > > > > > @@ -297,7 +297,7 @@ static int submit_fence_sync(struct msm_gem_submit *submit, bool no_implicit) > > > > > return ret; > > > > > } > > > > > > > > > > - if (no_implicit) > > > > > + if (!implicit_sync) > > > > > continue; > > > > > > > > > > ret = msm_gem_sync_object(&msm_obj->base, submit->ring->fctx, > > > > > @@ -768,7 +768,8 @@ int msm_ioctl_gem_submit(struct drm_device *dev, void *data, > > > > > if (ret) > > > > > goto out; > > > > > > > > > > - ret = submit_fence_sync(submit, !!(args->flags & MSM_SUBMIT_NO_IMPLICIT)); > > > > > + ret = submit_fence_sync(submit, (gpu->nr_rings > 1) && > > > > > + !(args->flags & MSM_SUBMIT_NO_IMPLICIT)); > > > > > if (ret) > > > > > goto out; > > > > > > > > > > -- > > > > > 2.26.2 > > > > > > > > > > > > > -- > > > > Daniel Vetter > > > > Software Engineer, Intel Corporation > > > > http://blog.ffwll.ch > > > > -- > > Daniel Vetter > > Software Engineer, Intel Corporation > > http://blog.ffwll.ch > > _______________________________________________ > > Freedreno mailing list > > Freedreno@lists.freedesktop.org > > https://lists.freedesktop.org/mailman/listinfo/freedreno -- Daniel Vetter Software Engineer, Intel Corporation http://blog.ffwll.ch