From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S934549AbeCHEPD (ORCPT ); Wed, 7 Mar 2018 23:15:03 -0500 Received: from mail-lf0-f65.google.com ([209.85.215.65]:38090 "EHLO mail-lf0-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S933890AbeCHEPC (ORCPT ); Wed, 7 Mar 2018 23:15:02 -0500 X-Google-Smtp-Source: AG47ELsEvr8Uzvsye6oYuI6Hb3cRXYlNF77O+8X2AqDIVYBmicEd/ShFC+MLhLAOwjAKiwTkKLXByjb5NpLxoWmzXKg= MIME-Version: 1.0 In-Reply-To: <52328144-3a2a-af03-273b-3a2f3bdadda6@redhat.com> References: <20180307110803.32418-1-ganapatrao.kulkarni@cavium.com> <3384d33f-c927-740a-97f1-b20775ef2c7b@redhat.com> <20180307143832.GJ3701@kernel.org> <52328144-3a2a-af03-273b-3a2f3bdadda6@redhat.com> From: Ganapatrao Kulkarni Date: Thu, 8 Mar 2018 09:44:59 +0530 Message-ID: Subject: Re: [PATCH] perf vendor events arm64: Enable JSON events for ThunderX2 B0 To: William Cohen Cc: Arnaldo Carvalho de Melo , mark.rutland@arm.com, Alexander Shishkin , John Garry , Will Deacon , linux-kernel@vger.kernel.org, Peter Zijlstra , Robert Richter , Ingo Molnar , jnair@caviumnetworks.com, Ganapatrao Kulkarni , Jiri Olsa , linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: 8bit X-MIME-Autoconverted: from quoted-printable to 8bit by mail.home.local id w284F7e5027664 On Thu, Mar 8, 2018 at 12:01 AM, William Cohen wrote: > On 03/07/2018 12:35 PM, Ganapatrao Kulkarni wrote: >> Hi Will Cohen, >> >> On Wed, Mar 7, 2018 at 8:08 PM, Arnaldo Carvalho de Melo >> wrote: >>> Em Wed, Mar 07, 2018 at 09:32:05AM -0500, William Cohen escreveu: >>>> On 03/07/2018 06:08 AM, Ganapatrao Kulkarni wrote: >>>>> There is MIDR change on ThunderX2 B0, adding an entry to mapfile >>>>> to enable JSON events for B0. >>>>> >>>>> Signed-off-by: Ganapatrao Kulkarni >>> >>> Ganapatrao, can you please take this in consideration and if agreeing >>> send a v2 patch? >>> >>> With that I can add an Acked-by: wcohen, Right? >>> >>> - Arnaldo >>>>> --- >>>>> tools/perf/pmu-events/arch/arm64/mapfile.csv | 1 + >>>>> 1 file changed, 1 insertion(+) >>>>> >>>>> diff --git a/tools/perf/pmu-events/arch/arm64/mapfile.csv b/tools/perf/pmu-events/arch/arm64/mapfile.csv >>>>> index e61c9ca..93c5d14 100644 >>>>> --- a/tools/perf/pmu-events/arch/arm64/mapfile.csv >>>>> +++ b/tools/perf/pmu-events/arch/arm64/mapfile.csv >>>>> @@ -13,4 +13,5 @@ >>>>> # >>>>> #Family-model,Version,Filename,EventType >>>>> 0x00000000420f5160,v1,cavium,core >>>>> +0x00000000430f0af0,v1,cavium,core >>>>> 0x00000000410fd03[[:xdigit:]],v1,cortex-a53,core >>>>> >>>> >>>> Hi, >>>> Like the cortex-a53 the last digit '0' of the match for the MIDR should be replaced with [[:xdigit:]] to allow for possible future revisions of chip: >> >> for arm64 implementation, bits 3:0(Revision) and bits 23:20(Variant) >> are ignored/dont-care. > > Thanks for pointing that out. See the code masking out those bits in linux/toos/perf/arch/util/header.c. For the ppc64 it just copies the equivalent of the MIDR including the revision bits. Thus, the need for regular expression matching to avoid having to create a new entry for each revision. It is same for arm64 too, there is no need to add an entry for every revision change, need to add when part number changes. This patch is not intended to add entry for revision change, the fact of the matter is that, there is complete MIDR change (vulcan to thunderx2) in B0. as per current arm64 implementation(.tools/perf/arch/arm64/util/header.c), it is not required to have any dontcare marking in mapfile for revision/variant bits. thanks Ganapat > > -Will > >> >>>> >>>> 0x00000000430f0af[[:xdigit:]],v1,cavium,core >>>> >>>> >>>> -Will Cohen >>> >> >> thanks >> Ganapat >>> _______________________________________________ >>> linux-arm-kernel mailing list >>> linux-arm-kernel@lists.infradead.org >>> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel >