Re: [PATCH v7 2/3] PCI: Enable PCIe Relaxed Ordering if supported

From: Alexander Duyck <alexander.duyck@gmail.com>
To: Ding Tianhong <dingtianhong@huawei.com>
Cc: Casey Leedom <leedom@chelsio.com>,
	Alex Williamson <alex.williamson@redhat.com>,
	Sinan Kaya <okaya@codeaurora.org>,
	"ashok.raj@intel.com" <ashok.raj@intel.com>,
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	"helgaas@kernel.org" <helgaas@kernel.org>,
	Michael Werner <werner@chelsio.com>,
	Ganesh GR <ganeshgr@chelsio.com>,
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	"patrick.j.cramer@intel.com" <patrick.j.cramer@intel.com>,
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Subject: Re: [PATCH v7 2/3] PCI: Enable PCIe Relaxed Ordering if supported
Date: Thu, 27 Jul 2017 10:49:25 -0700	[thread overview]
Message-ID: <CAKgT0UcqdRCwDDxD=22Q_jLuqz8KVHwH1-V45Aq-1WzQw=agcA@mail.gmail.com> (raw)
In-Reply-To: <75213fca-4522-2297-3cb8-338e643d3552@huawei.com>

On Wed, Jul 26, 2017 at 6:08 PM, Ding Tianhong <dingtianhong@huawei.com> wrote:
>
>
> On 2017/7/27 2:26, Casey Leedom wrote:
>>   By the way Ding, two issues:
>>
>>  1. Did we ever get any acknowledgement from either Intel or AMD
>>     on this patch?  I know that we can't ensure that, but it sure would
>>     be nice since the PCI Quirks that we're putting in affect their
>>     products.
>>
>
> Still no Intel and AMD guys has ack this, this is what I am worried about, should I
> ping some man again ?
>
> Thanks
> Ding

I probably wouldn't worry about it too much. If anything all this
patch is doing is disabling relaxed ordering on the platforms we know
have issues based on what Casey originally had. If nothing else we can
follow up once the patches are in the kernel and if somebody has an
issue then.

You can include my acked-by, but it is mostly related to how this
interacts with NICs, and not so much about the PCI chipsets
themselves.

Acked-by: Alexander Duyck <alexander.h.duyck@intel.com>