From: Viresh Kumar <viresh.kumar@linaro.org>
To: Pi-Cheng Chen <pi-cheng.chen@linaro.org>
Cc: Matthias Brugger <matthias.bgg@gmail.com>,
Rob Herring <robh+dt@kernel.org>,
"Rafael J. Wysocki" <rjw@rjwysocki.net>,
Thomas Petazzoni <thomas.petazzoni@free-electrons.com>,
Pawel Moll <pawel.moll@arm.com>,
Mark Rutland <mark.rutland@arm.com>,
Ian Campbell <ijc+devicetree@hellion.org.uk>,
Kumar Gala <galak@codeaurora.org>,
Catalin Marinas <catalin.marinas@arm.com>,
Will Deacon <will.deacon@arm.com>,
"Joe.C" <yingjoe.chen@mediatek.com>,
Eddie Huang <eddie.huang@mediatek.com>,
Howard Chen <ibanezchen@gmail.com>,
Ashwin Chaugule <ashwin.chaugule@linaro.org>,
Mike Turquette <mturquette@linaro.org>,
Chen Fan <fan.chen@mediatek.com>,
"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
"linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>,
Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
"linux-pm@vger.kernel.org" <linux-pm@vger.kernel.org>,
Linaro Kernel Mailman List <linaro-kernel@lists.linaro.org>,
linux-mediatek@lists.infradead.org
Subject: Re: [PATCH v2 1/4] cpufreq-dt: add clock domain and intermediate frequency support
Date: Thu, 5 Mar 2015 09:28:38 +0530 [thread overview]
Message-ID: <CAKohpo=zPsezGs8rqVzx3ChQkavs5z7eFMMETe12pc2mjm-8OA@mail.gmail.com> (raw)
In-Reply-To: <CALx668XCh46yMLajThuVzba9RRSxf+tEkNuMP9J7w-=vsZN8-Q@mail.gmail.com>
On 5 March 2015 at 09:02, Pi-Cheng Chen <pi-cheng.chen@linaro.org> wrote:
> In the case of Mediatek SoC, the intermediate frequency might not be one entry
> of OPP table. To elaborate, the source clock node of the CPUs/Cluster on
> Mediatek SoC is a mux. The mux has several PLLs as parents. When we are
> doing CPU frequency scaling, the mux should re-parent to another stable PLL,
> wait until the original parent PLL become stable, and then switch back to the
> original parent. In this case, we could but we might not want the intermediate
> frequency as part of OPP table. Therefore I save intermediate_freq instead of
> intermediate frequency index in the cpufreq_dt_platform_datat struct.
Hmm, I remember that discussion. Okay leave it as is.
> BTW, is this case that intermediate frequency is not necessarily be one entry
> of OPP table supported in the OPPv2 bindings?
Not yet, but will add a property for that.
next prev parent reply other threads:[~2015-03-05 3:58 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-03-04 8:49 [PATCH v2 0/4] cpufreq: add cpufreq driver for Mediatek MT8173 SoC pi-cheng.chen
2015-03-04 8:49 ` [PATCH v2 1/4] cpufreq-dt: add clock domain and intermediate frequency support pi-cheng.chen
2015-03-04 10:15 ` Viresh Kumar
2015-03-04 10:17 ` Viresh Kumar
2015-03-05 3:32 ` Pi-Cheng Chen
2015-03-05 3:58 ` Viresh Kumar [this message]
2015-03-05 7:28 ` Pi-Cheng Chen
2015-03-04 8:49 ` [PATCH v2 2/4] cpufreq: dt-bindings: add bindings for mtk-cpufreq driver pi-cheng.chen
2015-03-04 10:29 ` Viresh Kumar
2015-03-04 8:49 ` [PATCH v2 3/4] cpufreq: mediatek: add Mediatek cpufreq driver pi-cheng.chen
2015-03-04 11:09 ` Viresh Kumar
2015-03-05 7:27 ` Pi-Cheng Chen
2015-03-05 9:55 ` Viresh Kumar
2015-03-06 5:49 ` Pi-Cheng Chen
2015-03-10 2:50 ` Viresh Kumar
2015-03-11 10:53 ` Mark Brown
2015-03-11 11:03 ` Viresh Kumar
2015-03-11 11:42 ` Lucas Stach
2015-03-11 11:46 ` Viresh Kumar
2015-03-11 12:46 ` Mark Brown
2015-03-11 12:45 ` Mark Brown
2015-03-12 9:28 ` Viresh Kumar
2015-03-12 11:15 ` Pi-Cheng Chen
2015-03-18 6:59 ` Viresh Kumar
2015-03-09 16:28 ` Russell King - ARM Linux
2015-03-10 1:57 ` Pi-Cheng Chen
2015-03-04 8:49 ` [PATCH v2 4/4] ARM64: dts: mediatek: add cpufreq dts for MT8173 SoC pi-cheng.chen
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