From: Ard Biesheuvel <ard.biesheuvel@linaro.org>
To: Gabriele Paoloni <gabriele.paoloni@huawei.com>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
Hanjun Guo <hanjun.guo@linaro.org>,
Marcin Wojtas <mw@semihalf.com>,
Wangyijing <wangyijing@huawei.com>,
"linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>,
"linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>,
"liudongdong (C)" <liudongdong3@huawei.com>,
"linux-acpi@vger.kernel.org" <linux-acpi@vger.kernel.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH V6 3/5] PCI: thunder-pem: Allow to probe PEM-specific register range for ACPI case
Date: Thu, 14 Sep 2017 07:06:58 -0700 [thread overview]
Message-ID: <CAKv+Gu8x0j-O3WPE7Cvi4oX5J5Cq1vUhDNB_UdjE88eQh83DDA@mail.gmail.com> (raw)
In-Reply-To: <EE11001F9E5DDD47B7634E2F8A612F2E1F884340@lhreml507-mbx>
(remove most cc's)
Hi all,
Apologies for digging up this old thread.
I am currently looking into whether it is feasible to refactor some of
the ACPI PCI quirk code we have so it can apply to more instances of
the Synopsys Designware PCIe (i.e., for Marvell and Socionext SOCs),
which all suffer from the same issue that type 0 config TLPs are not
filtered before being sent out on the link, resulting in devices
appearing multiple times.
The pci-hisi.c quirk already appears to do exactly what would solve
the problem on other SoCs as well. So I will try to refactor this code
into something that I could propose for upstream, while probably
getting the ARM SBSA authors to offer some guidance that this IP must
not be used for new designs.
In any case, the chances of any such changes being acceptable upstream
are probably higher if we can reuse the exact same quirk as we have
already implemented for HiSilicon, so I wonder if anyone from Huawei
could comment on some questions I have:
- Why does the config space accessor override use 32-bit accesses only
for bus #0? Is that really necessary?
- Why does the Hisi quirk use different config base addresses for bus
#0 and the other buses? Is this simply because the firmware does not
use contiguous iATU windows for bus #0 and buses #1 and up? So is
there anything mapped in the 1 MB slice at the base of the respective
256 MB mappings that generate type1 config cycles?
Having just a shared set of config space accessor overrides would
already be an improvement, given that they can be shared with a DT
based driver for this IP in ECAM mode as well.
Thanks,
Ard.
next prev parent reply other threads:[~2017-09-14 14:07 UTC|newest]
Thread overview: 81+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-09-09 19:24 [PATCH V6 0/5] ECAM quirks handling for ARM64 platforms Tomasz Nowicki
2016-09-09 19:24 ` [PATCH V6 1/5] PCI/ACPI: Extend pci_mcfg_lookup() responsibilities Tomasz Nowicki
2016-09-09 19:24 ` [PATCH V6 2/5] PCI/ACPI: Check platform specific ECAM quirks Tomasz Nowicki
2016-09-12 22:24 ` Duc Dang
2016-09-12 22:47 ` Duc Dang
2016-09-13 5:58 ` Tomasz Nowicki
2016-09-13 6:37 ` Tomasz Nowicki
2016-09-13 2:36 ` Dongdong Liu
2016-09-13 6:32 ` Tomasz Nowicki
2016-09-13 11:38 ` Dongdong Liu
2016-09-14 12:40 ` Lorenzo Pieralisi
2016-09-15 10:58 ` Lorenzo Pieralisi
2016-09-16 9:02 ` Gabriele Paoloni
2016-09-16 12:27 ` Christopher Covington
2016-09-16 13:42 ` Gabriele Paoloni
2016-09-09 19:24 ` [PATCH V6 3/5] PCI: thunder-pem: Allow to probe PEM-specific register range for ACPI case Tomasz Nowicki
2016-09-19 18:09 ` Bjorn Helgaas
2016-09-20 7:23 ` Tomasz Nowicki
2016-09-20 13:33 ` Bjorn Helgaas
2016-09-20 13:40 ` Ard Biesheuvel
2016-09-20 14:05 ` Bjorn Helgaas
2016-09-20 15:09 ` Ard Biesheuvel
2016-09-20 19:17 ` Bjorn Helgaas
2016-09-21 14:05 ` Lorenzo Pieralisi
2016-09-21 18:04 ` Bjorn Helgaas
2016-09-21 18:58 ` Duc Dang
2016-09-21 19:18 ` Bjorn Helgaas
2016-09-23 10:53 ` Tomasz Nowicki
2016-09-22 9:49 ` Lorenzo Pieralisi
2016-09-22 11:10 ` Gabriele Paoloni
2016-09-22 12:44 ` Lorenzo Pieralisi
2016-09-22 18:31 ` Bjorn Helgaas
2016-09-22 22:10 ` Bjorn Helgaas
2016-09-23 10:11 ` Lorenzo Pieralisi
2016-09-23 10:58 ` Gabriele Paoloni
2017-09-14 14:06 ` Ard Biesheuvel [this message]
2017-09-26 8:23 ` Gabriele Paoloni
2016-09-22 14:20 ` Christopher Covington
2016-09-21 14:10 ` Gabriele Paoloni
2016-09-21 18:59 ` Bjorn Helgaas
2016-09-22 11:12 ` Gabriele Paoloni
2016-09-09 19:24 ` [PATCH V6 4/5] PCI: thunder: Enable ACPI PCI controller for ThunderX pass2.x silicon version Tomasz Nowicki
2016-09-19 15:45 ` Bjorn Helgaas
2016-09-20 7:06 ` Tomasz Nowicki
2016-09-20 13:08 ` Bjorn Helgaas
2016-09-21 8:05 ` Tomasz Nowicki
2016-09-09 19:24 ` [PATCH V6 5/5] PCI: thunder: Enable ACPI PCI controller for ThunderX pass1.x " Tomasz Nowicki
2016-09-09 19:30 ` [PATCH V6 0/5] ECAM quirks handling for ARM64 platforms Tomasz Nowicki
2016-09-20 19:26 ` Bjorn Helgaas
2016-09-21 1:15 ` cov
2016-09-21 13:11 ` Bjorn Helgaas
2016-09-21 14:07 ` Sinan Kaya
2016-09-21 17:31 ` Bjorn Helgaas
2016-09-21 17:34 ` Sinan Kaya
2016-09-21 22:38 ` [PATCHv2] PCI: QDF2432 32 bit config space accessors Christopher Covington
2016-10-31 21:48 ` Bjorn Helgaas
2016-11-01 13:06 ` cov
2016-11-02 16:08 ` Bjorn Helgaas
2016-11-02 16:36 ` Sinan Kaya
2016-11-03 14:00 ` Bjorn Helgaas
2016-11-03 16:58 ` Sinan Kaya
2016-11-03 17:06 ` Sinan Kaya
2016-11-03 20:43 ` Bjorn Helgaas
2016-11-03 23:49 ` Sinan Kaya
2016-12-02 4:58 ` Jon Masters
2016-11-02 16:41 ` Bjorn Helgaas
2016-11-09 19:25 ` Christopher Covington
2016-11-09 20:06 ` Bjorn Helgaas
2016-11-09 20:29 ` Ard Biesheuvel
2016-11-09 22:49 ` Bjorn Helgaas
2016-11-10 10:25 ` Ard Biesheuvel
2016-11-10 13:57 ` Lorenzo Pieralisi
2016-11-10 17:42 ` Bjorn Helgaas
2016-12-02 5:12 ` Jon Masters
2016-09-21 22:40 ` [PATCH V6 0/5] ECAM quirks handling for ARM64 platforms Christopher Covington
2016-09-22 23:08 ` Bjorn Helgaas
2016-09-23 18:41 ` Christopher Covington
2016-09-23 19:17 ` Bjorn Helgaas
2016-09-23 19:22 ` Christopher Covington
2016-11-24 11:05 ` [PATCH V6 1/1] ARM64/PCI: Manage controller-specific information on the host controller basis Tomasz Nowicki
2016-11-29 23:40 ` Bjorn Helgaas
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