From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.1 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_PASS, URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1D89DC282C3 for ; Thu, 24 Jan 2019 11:26:29 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id DC5DD20811 for ; Thu, 24 Jan 2019 11:26:28 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=linaro.org header.i=@linaro.org header.b="YIifzmPE" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727867AbfAXL01 (ORCPT ); Thu, 24 Jan 2019 06:26:27 -0500 Received: from mail-it1-f196.google.com ([209.85.166.196]:38978 "EHLO mail-it1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727617AbfAXL00 (ORCPT ); Thu, 24 Jan 2019 06:26:26 -0500 Received: by mail-it1-f196.google.com with SMTP id a6so3863270itl.4 for ; Thu, 24 Jan 2019 03:26:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=wYYDIZC0ZN9AMXQL3vOyxwdVx9TvTCIi6QQpdmvhI+4=; b=YIifzmPEIpkCk/CFNx0FQasSOzULmpRwmmbHtG9bdFFTqd7hPxDKOAhkYWOshfMG9U 5iLJVXV/qbSb6l2jK7MhsghJsMJVvHTcGUktnsFJQIF/+/10c8vRnsRzCAKZHHDqsF1N 6GjY2eEtXbAew9VwFbewbQms/uGqSHoDtQQmE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=wYYDIZC0ZN9AMXQL3vOyxwdVx9TvTCIi6QQpdmvhI+4=; b=H2/twtE50SlEomehV6VR0spKEr4AEreuIcdHpR6x8YkuS8bmUWd44qNEVswbbzdFae WoXES8OZ4Z4n309iRxTN0n/fEVOIPqxvIrZtlE1wy98zdG4gza4eWNj31Uejgq4Kwjvx u7V8N9XGelrGu7HVcYjcAho8vH/WL1Hb5Mh7mEq8AEg7pS6tCXZLZa+Vec+GwZvBn7sN VDXBvTDM0ASXrB+LfYEjqum0R5SkVJNItTecfoAbezwJnoV4gBfveRf8EkinYojjy/9r eaYvU+lD2rKGc5rhM8P++8REZSrLWy/7hinvhIOeomku+qd8Tw9HPHmfjaTZ7RBepUi/ 37hQ== X-Gm-Message-State: AJcUukfLB15W1BgxajDezQqXANYhOxXUqOxwTE/bxzATuB6DzUw+OslS Hs2H4S85c4iZI6WCVVDJvn9VlUKLpjqCEJThsvFLvA== X-Google-Smtp-Source: ALg8bN5Qirvee4cj0+G+OHBW4ZJWfWnzhIaOdLarAZ+wKU1LOI4NQw6yzf2KnVatfnJc5KOYvnIO+D4XRuts4eo59E8= X-Received: by 2002:a02:183:: with SMTP id 3mr4017791jak.130.1548329185953; Thu, 24 Jan 2019 03:26:25 -0800 (PST) MIME-Version: 1.0 References: <850b6aee-0040-c333-b125-45211c18ada5@daenzer.net> <047667fd-17be-1c37-5d2a-26768cfd6ab8@daenzer.net> <20190123071521.GB20526@infradead.org> <20190123164428.GA9367@infradead.org> <20190124091316.GA22796@infradead.org> <953e5e5f-5d47-d6df-40df-c8c94db5447f@amd.com> <57590a48-4629-e2a1-8673-ce9eb2ec210b@amd.com> In-Reply-To: <57590a48-4629-e2a1-8673-ce9eb2ec210b@amd.com> From: Ard Biesheuvel Date: Thu, 24 Jan 2019 12:26:14 +0100 Message-ID: Subject: Re: [RFC PATCH] drm: disable WC optimization for cache coherent devices on non-x86 To: "Koenig, Christian" Cc: Christoph Hellwig , Alex Deucher , =?UTF-8?Q?Michel_D=C3=A4nzer?= , Maxime Ripard , Will Deacon , Linux Kernel Mailing List , amd-gfx list , David Airlie , "Huang, Ray" , dri-devel , Michael Ellerman , "Zhang, Jerry" , "Deucher, Alexander" , Sean Paul , linux-arm-kernel Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, 24 Jan 2019 at 12:23, Koenig, Christian wrote: > > Am 24.01.19 um 10:59 schrieb Ard Biesheuvel: > > [SNIP] > > This is *exactly* my point the whole time. > > > > The current code has > > > > static inline bool drm_arch_can_wc_memory(void) > > { > > #if defined(CONFIG_PPC) && !defined(CONFIG_NOT_COHERENT_CACHE) > > return false; > > > > which means the optimization is disabled *unless the system is > > non-cache coherent* > > > > So if you have reports that the optimization works on some PowerPC, it > > must be non-cache coherent PowerPC, because that is the only place > > where it is enabled in the first place. > > > >> The only problematic here actually seems to be ARM, so you should > >> probably just add an "#ifdef .._ARM return false;". > >> > > ARM/arm64 does not have a Kconfig symbol like > > CONFIG_NOT_COHERENT_CACHE, so we can only disable it everywhere. If > > there are non-coherent ARM systems that are currently working in the > > same way as those non-coherent PowerPC systems, we will break them by > > doing this. > > Summing the things I've read so far for ARM up I actually think it > depends on a runtime configuration and not on compile time one. > > So the whole idea of providing the device to the drm_*_can_wc_memory() > function isn't so far fetched. > Thank you. > But for now I do prefer working and slightly slower system over broken > one, so I think we should just disable this on ARM for now. > Again, this is not about non-cache coherent being slower without the optimization, it is about non-cache coherent likely not working *at all* unless the optimization is enabled. Otherwise, the driver will vmap() DMA pages with cacheable attributes, while the non-cache coherent device uses uncached attributes, breaking coherency.