From: Andrew Bresticker <abrestic@chromium.org>
To: Qais Yousef <qais.yousef@imgtec.com>
Cc: Ralf Baechle <ralf@linux-mips.org>,
Thomas Gleixner <tglx@linutronix.de>,
Jason Cooper <jason@lakedaemon.net>,
Jeffrey Deans <jeffrey.deans@imgtec.com>,
Markos Chandras <markos.chandras@imgtec.com>,
Paul Burton <paul.burton@imgtec.com>,
Jonas Gorski <jogo@openwrt.org>,
John Crispin <blogic@openwrt.org>,
David Daney <ddaney.cavm@gmail.com>,
Linux-MIPS <linux-mips@linux-mips.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH 21/24] irqchip: mips-gic: Support local interrupts
Date: Wed, 17 Sep 2014 14:09:00 -0700 [thread overview]
Message-ID: <CAL1qeaEikmx3bsqNz1bvkhmyPU=GNuSGyMRQvcgxHYb2yj-aog@mail.gmail.com> (raw)
In-Reply-To: <CAL1qeaFt5ZBauD38WMPB7WLkOqkTgtfO-gLKo3of7C_V-53eLA@mail.gmail.com>
On Wed, Sep 17, 2014 at 10:40 AM, Andrew Bresticker
<abrestic@chromium.org> wrote:
> On Wed, Sep 17, 2014 at 2:50 AM, Qais Yousef <qais.yousef@imgtec.com> wrote:
>> On 09/16/2014 12:51 AM, Andrew Bresticker wrote:
>>>
>>> The MIPS GIC supports 7 local interrupts, 2 of which are the GIC
>>> local watchdog and count/compare timer. The remainder are CPU
>>> interrupts which may optionally be re-routed through the GIC.
>>> GIC hardware IRQs 0-6 are now used for local interrupts while
>>> hardware IRQs 7+ are used for external (shared) interrupts.
>>>
>>> Note that the 5 CPU interrupts may not be re-routable through
>>> the GIC. In that case mapping will fail and the vectors reported
>>> in C0_IntCtl should be used instead. gic_get_c0_compare_int() and
>>> gic_get_c0_perfcount_int() will return the correct IRQ number to
>>> use for the C0 timer and perfcounter interrupts based on the
>>> routability of those interrupts through the GIC.
>>>
>>> Malta, SEAD-3, and the GIC clockevent driver have been updated
>>> to use local interrupts and the R4K clockevent driver has been
>>> updated to poll for C0 timer interrupts through the GIC when
>>> the GIC is present.
>>>
>>> Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
>
>>> diff --git a/arch/mips/include/asm/mips-boards/maltaint.h
>>> b/arch/mips/include/asm/mips-boards/maltaint.h
>>> index bdd6f39..38b06a0 100644
>>> --- a/arch/mips/include/asm/mips-boards/maltaint.h
>>> +++ b/arch/mips/include/asm/mips-boards/maltaint.h
>>> @@ -10,6 +10,8 @@
>>> #ifndef _MIPS_MALTAINT_H
>>> #define _MIPS_MALTAINT_H
>>> +#include <asm/gic.h>
>>> +
>>
>>
>> nit: I think gic.h should be split to driver/irqchip/irq-mips-gic.h for
>> private definitions and include/linux/irqchip/irq-mips-gic.h for
>> exported/public definitions.
>
> Yup, I was planning on doing this in the next series :). Malta and
> the clockevent/clocksource driver need to get cleaned up first though,
> so that they don't have to use the private register definitions.
>
>>> diff --git a/drivers/irqchip/irq-mips-gic.c
>>> b/drivers/irqchip/irq-mips-gic.c
>>> index 6682a4e..3abe310 100644
>>> --- a/drivers/irqchip/irq-mips-gic.c
>>> +++ b/drivers/irqchip/irq-mips-gic.c
>
>>> @@ -95,12 +96,39 @@ cycle_t gic_read_compare(void)
>>> }
>>> #endif
>>> +static bool gic_local_irq_is_routable(int intr)
>>> +{
>>> + u32 vpe_ctl;
>>> +
>>> + /* All local interrupts are routable in EIC mode. */
>>> + if (cpu_has_veic)
>>> + return true;
>>> +
>>> + GICREAD(GIC_REG(VPE_LOCAL, GIC_VPE_CTL), vpe_ctl);
>>> + switch (intr) {
>>> + case GIC_LOCAL_INT_TIMER:
>>> + return vpe_ctl & GIC_VPE_CTL_TIMER_RTBL_MSK;
>>> + case GIC_LOCAL_INT_PERFCTR:
>>> + return vpe_ctl & GIC_VPE_CTL_PERFCNT_RTBL_MSK;
>>> + case GIC_LOCAL_INT_FDC:
>>> + return vpe_ctl & GIC_VPE_CTL_FDC_RTBL_MSK;
>>> + case GIC_LOCAL_INT_SWINT0:
>>> + case GIC_LOCAL_INT_SWINT1:
>>> + /*
>>> + * SWINT{0,1} are not routable in non-EIC mode, regardless
>>> + * of the setting of SWINT_ROUTABLE.
>>> + */
>>> + return false;
>>
>>
>> Hmm AFAIK they are routable. Actually from hard reset they're automatically
>> routed to vpe0 pin 0 which caught me a number of times when trying to use
>> software interrupt on hardware that has GIC. When setting software interrupt
>> I was seeing pin 0 going high too and thought it's a hardware bug for a
>> while.
>
> Interesting, the interAptiv User's Manual I have, in section 9.4.7.1,
> says: "Note that Software Interrupts from the VPE are routed
> internally by the CPU in vectored interrupt mode, and are only routed
> through the GIC when the GIC is in EIC mode, regardless of the
> GIC_VPEi_CTL register." IIRC, there's a similar statement in the
> proAptiv manual as well. I didn't play with the SWINT bits myself, so
> I wouldn't be surprised if that's wrong :).
>
>> I think all local interrupts should be masked at GIC initialisation except
>> for timer interrupt. I was preparing a set of patches for GIC but you beat
>> me into it :)
>
> If SWINT gets routed both through the GIC and directly to the CPU,
> then that's probably the best thing to do. I suspect we'll also want
> to leave the performance counter interrupt unmasked too, since,
> unfortunately, both the HW perf event driver and oprofile do not use
> the percpu IRQ API.
Instead of leaving those two unmasked, perhaps the better thing to do
is to have a separate irq_chip which masks/unmasks on all VPEs.
next prev parent reply other threads:[~2014-09-17 21:09 UTC|newest]
Thread overview: 40+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-09-15 23:51 [PATCH 00/24] MIPS GIC cleanup, part 1 Andrew Bresticker
2014-09-15 23:51 ` [PATCH 01/24] MIPS: Always use IRQ domains for CPU IRQs Andrew Bresticker
2014-09-15 23:51 ` [PATCH 02/24] MIPS: Rename mips_cpu_intc_init() -> mips_cpu_irq_of_init() Andrew Bresticker
2014-09-15 23:51 ` [PATCH 03/24] MIPS: Provide a generic plat_irq_dispatch Andrew Bresticker
2014-09-17 8:56 ` Qais Yousef
2014-09-17 16:36 ` Andrew Bresticker
2014-09-15 23:51 ` [PATCH 04/24] MIPS: Set vint handler when mapping CPU interrupts Andrew Bresticker
2014-09-15 23:51 ` [PATCH 05/24] MIPS: i8259: Use IRQ domains Andrew Bresticker
2014-09-15 23:51 ` [PATCH 06/24] MIPS: Add hook to get C0 performance counter interrupt Andrew Bresticker
2014-09-15 23:51 ` [PATCH 07/24] MIPS: smp-cps: Enable all hardware interrupts on secondary CPUs Andrew Bresticker
2014-09-15 23:51 ` [PATCH 08/24] MIPS: Remove gic_{enable,disable}_interrupt() Andrew Bresticker
2014-09-15 23:51 ` [PATCH 09/24] MIPS: sead3: Remove sead3-serial.c Andrew Bresticker
2014-09-15 23:51 ` [PATCH 10/24] MIPS: sead3: Do not overlap CPU/GIC IRQ ranges Andrew Bresticker
2014-09-15 23:51 ` [PATCH 11/24] MIPS: Malta: Move MSC01 interrupt base Andrew Bresticker
2014-09-15 23:51 ` [PATCH 12/24] MIPS: Move MIPS_GIC_IRQ_BASE into platform irq.h Andrew Bresticker
2014-09-15 23:51 ` [PATCH 13/24] MIPS: Move GIC to drivers/irqchip/ Andrew Bresticker
2014-09-15 23:51 ` [PATCH 14/24] irqchip: mips-gic: Implement generic irq_ack/irq_eoi callbacks Andrew Bresticker
2014-09-17 9:14 ` Qais Yousef
2014-09-17 17:14 ` Andrew Bresticker
2014-09-15 23:51 ` [PATCH 15/24] irqchip: mips-gic: Implement irq_set_type callback Andrew Bresticker
2014-09-15 23:51 ` [PATCH 16/24] irqchip: mips-gic: Fix gic_set_affinity() return value Andrew Bresticker
2014-09-15 23:51 ` [PATCH 17/24] irqchip: mips-gic: Use IRQ domains Andrew Bresticker
2014-09-15 23:51 ` [PATCH 18/24] irqchip: mips-gic: Stop using per-platform mapping tables Andrew Bresticker
2014-09-17 9:21 ` Qais Yousef
2014-09-15 23:51 ` [PATCH 19/24] irqchip: mips-gic: Probe for number of external interrupts Andrew Bresticker
2014-09-15 23:51 ` [PATCH 20/24] irqchip: mips-gic: Use separate edge/level irq_chips Andrew Bresticker
2014-09-17 9:24 ` Qais Yousef
2014-09-17 17:15 ` Andrew Bresticker
2014-09-15 23:51 ` [PATCH 21/24] irqchip: mips-gic: Support local interrupts Andrew Bresticker
2014-09-17 9:50 ` Qais Yousef
2014-09-17 17:40 ` Andrew Bresticker
2014-09-17 21:09 ` Andrew Bresticker [this message]
2014-09-18 6:57 ` Qais Yousef
2014-09-15 23:51 ` [PATCH 22/24] irqchip: mips-gic: Remove unnecessary globals Andrew Bresticker
2014-09-15 23:51 ` [PATCH 23/24] MIPS: Malta: Use generic plat_irq_dispatch Andrew Bresticker
2014-09-15 23:51 ` [PATCH 24/24] MIPS: sead3: " Andrew Bresticker
2014-09-17 10:20 ` [PATCH 00/24] MIPS GIC cleanup, part 1 Qais Yousef
2014-09-17 17:42 ` Andrew Bresticker
2014-09-18 7:08 ` Qais Yousef
2014-09-17 14:07 ` Jason Cooper
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