From: Andy Lutomirski <luto@kernel.org>
To: Borislav Petkov <bp@alien8.de>
Cc: Andy Lutomirski <luto@kernel.org>, X86 ML <x86@kernel.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
Linus Torvalds <torvalds@linux-foundation.org>,
Andrew Morton <akpm@linux-foundation.org>,
Mel Gorman <mgorman@suse.de>,
"linux-mm@kvack.org" <linux-mm@kvack.org>,
Nadav Amit <nadav.amit@gmail.com>, Rik van Riel <riel@redhat.com>,
Dave Hansen <dave.hansen@intel.com>,
Arjan van de Ven <arjan@linux.intel.com>,
Peter Zijlstra <peterz@infradead.org>
Subject: Re: [PATCH v3 05/11] x86/mm: Track the TLB's tlb_gen and update the flushing algorithm
Date: Thu, 22 Jun 2017 08:55:36 -0700 [thread overview]
Message-ID: <CALCETrUPqG-YcneqSqUYzWTJbm2Ae0Nj3K0MuS0cKYeD0yWhuw@mail.gmail.com> (raw)
In-Reply-To: <20170622145914.tzqdulshlssiywj4@pd.tnic>
On Thu, Jun 22, 2017 at 7:59 AM, Borislav Petkov <bp@alien8.de> wrote:
> On Thu, Jun 22, 2017 at 07:48:21AM -0700, Andy Lutomirski wrote:
>> On Thu, Jun 22, 2017 at 12:24 AM, Borislav Petkov <bp@alien8.de> wrote:
>> > On Wed, Jun 21, 2017 at 07:46:05PM -0700, Andy Lutomirski wrote:
>> >> > I'm certainly still missing something here:
>> >> >
>> >> > We have f->new_tlb_gen and mm_tlb_gen to control the flushing, i.e., we
>> >> > do once
>> >> >
>> >> > bump_mm_tlb_gen(mm);
>> >> >
>> >> > and once
>> >> >
>> >> > info.new_tlb_gen = bump_mm_tlb_gen(mm);
>> >> >
>> >> > and in both cases, the bumping is done on mm->context.tlb_gen.
>> >> >
>> >> > So why isn't that enough to do the flushing and we have to consult
>> >> > info.new_tlb_gen too?
>> >>
>> >> The issue is a possible race. Suppose we start at tlb_gen == 1 and
>> >> then two concurrent flushes happen. The first flush is a full flush
>> >> and sets tlb_gen to 2. The second is a partial flush and sets tlb_gen
>> >> to 3. If the second flush gets propagated to a given CPU first and it
>> >
>> > Maybe I'm still missing something, which is likely...
>> >
>> > but if the second flush gets propagated to the CPU first, the CPU will
>> > have local tlb_gen 1 and thus enforce a full flush anyway because we
>> > will go 1 -> 3 on that particular CPU. Or?
>> >
>>
>> Yes, exactly. Which means I'm probably just misunderstanding your
>> original question. Can you re-ask it?
>
> Ah, simple: we control the flushing with info.new_tlb_gen and
> mm->context.tlb_gen. I.e., this check:
>
>
> if (f->end != TLB_FLUSH_ALL &&
> f->new_tlb_gen == local_tlb_gen + 1 &&
> f->new_tlb_gen == mm_tlb_gen) {
>
> why can't we write:
>
> if (f->end != TLB_FLUSH_ALL &&
> mm_tlb_gen == local_tlb_gen + 1)
>
> ?
Ah, I thought you were asking about why I needed mm_tlb_gen ==
local_tlb_gen + 1. This is just an optimization, or at least I hope
it is. The idea is that, if we know that another flush is coming, it
seems likely that it would be faster to do a full flush and increase
local_tlb_gen all the way to mm_tlb_gen rather than doing a partial
flush, increasing local_tlb_gen to something less than mm_tlb_gen, and
needing to flush again very soon.
>
> If mm_tlb_gen is + 2, then we'll do a full flush, if it is + 1, then
> partial.
>
> If the second flush, as you say is a partial one and still gets
> propagated first, the check will force a full flush anyway.
>
> When the first flush propagates after the second, we'll ignore it
> because local_tlb_gen has advanced adready due to the second flush.
>
> As a matter of fact, we could simplify the logic: if local_tlb_gen is
> only mm_tlb_gen - 1, then do the requested flush type.
Hmm. I'd be nervous that there are more subtle races if we do this.
For example, suppose that a partial flush increments tlb_gen from 1 to
2 and a full flush increments tlb_gen from 2 to 3. Meanwhile, the CPU
is busy switching back and forth between mms, so the partial flush
sees the cpu set in mm_cpumask but the full flush doesn't see the cpu
set in mm_cpumask. The flush IPI hits after a switch_mm_irqs_off()
call notices the change from 1 to 2. switch_mm_irqs_off() will do a
full flush and increment the local tlb_gen to 2, and the IPI handler
for the partial flush will see local_tlb_gen == mm_tlb_gen - 1
(because local_tlb_gen == 2 and mm_tlb_gen == 3) and do a partial
flush. The problem here is that it's not obvious to me that this
actually ends up flushing everything that's needed. Maybe all the
memory ordering gets this right, but I can imagine scenarios in which
switch_mm_irqs_off() does its flush early enough that the TLB picks up
an entry that was supposed to get zapped by the full flush.
IOW it *might* be valid, but I think it would need very careful review
and documentation.
--Andy
next prev parent reply other threads:[~2017-06-22 15:56 UTC|newest]
Thread overview: 78+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-06-21 5:22 [PATCH v3 00/11] PCID and improved laziness Andy Lutomirski
2017-06-21 5:22 ` [PATCH v3 01/11] x86/mm: Don't reenter flush_tlb_func_common() Andy Lutomirski
2017-06-21 8:01 ` Thomas Gleixner
2017-06-21 8:49 ` Borislav Petkov
2017-06-21 15:15 ` Andy Lutomirski
2017-06-21 23:26 ` Nadav Amit
2017-06-22 2:27 ` Andy Lutomirski
2017-06-22 7:32 ` Ingo Molnar
2017-06-21 5:22 ` [PATCH v3 02/11] x86/ldt: Simplify LDT switching logic Andy Lutomirski
2017-06-21 8:03 ` Thomas Gleixner
2017-06-21 9:40 ` Borislav Petkov
2017-06-22 11:08 ` [tip:x86/mm] x86/ldt: Simplify the " tip-bot for Andy Lutomirski
2017-06-21 5:22 ` [PATCH v3 03/11] x86/mm: Remove reset_lazy_tlbstate() Andy Lutomirski
2017-06-21 8:03 ` Thomas Gleixner
2017-06-21 9:50 ` Borislav Petkov
2017-06-22 11:08 ` [tip:x86/mm] " tip-bot for Andy Lutomirski
2017-06-21 5:22 ` [PATCH v3 04/11] x86/mm: Give each mm TLB flush generation a unique ID Andy Lutomirski
2017-06-21 8:05 ` Thomas Gleixner
2017-06-21 10:33 ` Borislav Petkov
2017-06-21 15:23 ` Andy Lutomirski
2017-06-21 17:06 ` Borislav Petkov
2017-06-21 17:43 ` Borislav Petkov
2017-06-22 2:34 ` Andy Lutomirski
2017-06-21 5:22 ` [PATCH v3 05/11] x86/mm: Track the TLB's tlb_gen and update the flushing algorithm Andy Lutomirski
2017-06-21 8:32 ` Thomas Gleixner
2017-06-21 15:11 ` Andy Lutomirski
2017-06-21 18:44 ` Borislav Petkov
2017-06-22 2:46 ` Andy Lutomirski
2017-06-22 7:24 ` Borislav Petkov
2017-06-22 14:48 ` Andy Lutomirski
2017-06-22 14:59 ` Borislav Petkov
2017-06-22 15:55 ` Andy Lutomirski [this message]
2017-06-22 17:22 ` Borislav Petkov
2017-06-22 18:08 ` Andy Lutomirski
2017-06-23 8:42 ` Borislav Petkov
2017-06-23 15:46 ` Andy Lutomirski
2017-06-21 5:22 ` [PATCH v3 06/11] x86/mm: Rework lazy TLB mode and TLB freshness tracking Andy Lutomirski
2017-06-21 9:01 ` Thomas Gleixner
2017-06-21 16:04 ` Andy Lutomirski
2017-06-21 17:29 ` Borislav Petkov
2017-06-22 14:50 ` Borislav Petkov
2017-06-22 17:47 ` Andy Lutomirski
2017-06-22 19:05 ` Borislav Petkov
2017-07-27 19:53 ` Andrew Banman
2017-07-28 2:05 ` Andy Lutomirski
2017-06-23 13:34 ` Boris Ostrovsky
2017-06-23 15:22 ` Andy Lutomirski
2017-06-21 5:22 ` [PATCH v3 07/11] x86/mm: Stop calling leave_mm() in idle code Andy Lutomirski
2017-06-21 9:22 ` Thomas Gleixner
2017-06-21 15:16 ` Andy Lutomirski
2017-06-23 9:07 ` Borislav Petkov
2017-06-21 5:22 ` [PATCH v3 08/11] x86/mm: Disable PCID on 32-bit kernels Andy Lutomirski
2017-06-21 9:26 ` Thomas Gleixner
2017-06-23 9:24 ` Borislav Petkov
2017-06-21 5:22 ` [PATCH v3 09/11] x86/mm: Add nopcid to turn off PCID Andy Lutomirski
2017-06-21 9:27 ` Thomas Gleixner
2017-06-23 9:34 ` Borislav Petkov
2017-06-21 5:22 ` [PATCH v3 10/11] x86/mm: Enable CR4.PCIDE on supported systems Andy Lutomirski
2017-06-21 9:39 ` Thomas Gleixner
2017-06-21 13:40 ` Thomas Gleixner
2017-06-21 20:34 ` Andy Lutomirski
2017-06-23 11:50 ` Borislav Petkov
2017-06-23 15:28 ` Andy Lutomirski
2017-06-23 13:35 ` Boris Ostrovsky
2017-06-21 5:22 ` [PATCH v3 11/11] x86/mm: Try to preserve old TLB entries using PCID Andy Lutomirski
2017-06-21 13:38 ` Thomas Gleixner
2017-06-21 13:40 ` Thomas Gleixner
2017-06-22 2:57 ` Andy Lutomirski
2017-06-22 12:21 ` Thomas Gleixner
2017-06-22 18:12 ` Andy Lutomirski
2017-06-22 21:22 ` Thomas Gleixner
2017-06-23 3:09 ` Andy Lutomirski
2017-06-23 7:29 ` Thomas Gleixner
2017-06-22 16:09 ` Nadav Amit
2017-06-22 18:10 ` Andy Lutomirski
2017-06-26 15:58 ` Borislav Petkov
2017-06-21 18:23 ` [PATCH v3 00/11] PCID and improved laziness Linus Torvalds
2017-06-22 5:19 ` Andy Lutomirski
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