From: Andy Lutomirski <luto@amacapital.net>
To: Thomas Gleixner <tglx@linutronix.de>
Cc: LKML <linux-kernel@vger.kernel.org>, X86 ML <x86@kernel.org>,
Peter Zijlstra <peterz@infradead.org>,
Kyle Huey <khuey@kylehuey.com>, Andy Lutomirski <luto@kernel.org>
Subject: Re: [patch 2/3] x86/process: Optimize TIF_BLOCKSTEP switch
Date: Thu, 15 Dec 2016 09:28:52 -0800 [thread overview]
Message-ID: <CALCETrUaVrHYS5Jf3+ez4LN_X=_LFmVxhFwkn9JnKcJXGX6uZQ@mail.gmail.com> (raw)
In-Reply-To: <20161215164240.813682510@linutronix.de>
On Thu, Dec 15, 2016 at 8:44 AM, Thomas Gleixner <tglx@linutronix.de> wrote:
> Provide and use a seperate helper for toggling the DEBUGCTLMSR_BTF bit
> instead of doing it open coded with a branch and eventually evaluating
> boot_cpu_data twice.
>
> x86_64:
> 3694 8505 16 12215 2fb7 Before
> 3662 8505 16 12183 2f97 After
>
> i386:
> 5986 9388 1804 17178 431a Before
> 5906 9388 1804 17098 42ca After
>
> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
> ---
> arch/x86/include/asm/processor.h | 12 ++++++++++++
> arch/x86/kernel/process.c | 10 ++--------
> 2 files changed, 14 insertions(+), 8 deletions(-)
>
> --- a/arch/x86/include/asm/processor.h
> +++ b/arch/x86/include/asm/processor.h
> @@ -676,6 +676,18 @@ static inline void update_debugctlmsr(un
> wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr);
> }
>
> +static inline void toggle_debugctlmsr(unsigned long mask)
> +{
> + unsigned long msrval;
> +
> +#ifndef CONFIG_X86_DEBUGCTLMSR
> + if (boot_cpu_data.x86 < 6)
> + return;
> +#endif
> + rdmsrl(MSR_IA32_DEBUGCTLMSR, msrval);
> + wrmsrl(MSR_IA32_DEBUGCTLMSR, msrval ^ mask);
> +}
> +
This scares me. If the MSR ever gets out of sync with the TI flag,
this will malfunction. And IIRC the MSR is highly magical and the CPU
clears it all by itself under a variety of not-so-well documented
circumstances.
How about adding a real feature bit and doing:
if (!static_cpu_has(X86_FEATURE_BLOCKSTEP))
return;
rdmsrl(MSR_IA32_DEBUGCTLMSR, msrval);
msrval &= DEBUGCTLMSR_BTF;
msrval |= (tifn >> TIF_BLOCKSTEP) << DEBUGCTLMSR_BIT;
--Andy
next prev parent reply other threads:[~2016-12-15 17:29 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-12-15 16:44 [patch 0/3] x86/process: Optimize __switch_to_extra() Thomas Gleixner
2016-12-15 16:44 ` [patch 2/3] x86/process: Optimize TIF_BLOCKSTEP switch Thomas Gleixner
2016-12-15 17:28 ` Andy Lutomirski [this message]
2016-12-16 8:47 ` Thomas Gleixner
2016-12-16 19:22 ` Andy Lutomirski
2016-12-15 16:44 ` [patch 1/3] x86/process: Optimize TIF checks in switch_to_extra() Thomas Gleixner
2016-12-15 17:20 ` Peter Zijlstra
2016-12-15 17:26 ` Thomas Gleixner
2016-12-15 17:33 ` Peter Zijlstra
2016-12-15 17:24 ` Andy Lutomirski
2016-12-15 16:44 ` [patch 3/3] x86/process: Optimize TIF_NOTSC switch Thomas Gleixner
2016-12-15 17:31 ` Andy Lutomirski
2016-12-16 8:50 ` Thomas Gleixner
2016-12-16 18:34 ` Andy Lutomirski
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