From: Andy Lutomirski <luto@kernel.org>
To: Arvind Sankar <nivedita@alum.mit.edu>
Cc: Thomas Gleixner <tglx@linutronix.de>,
Ingo Molnar <mingo@redhat.com>, Borislav Petkov <bp@alien8.de>,
"Kirill A. Shutemov" <kirill.shutemov@linux.intel.com>,
Linus Torvalds <torvalds@linux-foundation.org>,
X86 ML <x86@kernel.org>, LKML <linux-kernel@vger.kernel.org>
Subject: Re: x86: Question about state of general purpose registers on switch to 64-bit mode
Date: Sat, 23 May 2020 10:19:52 -0700 [thread overview]
Message-ID: <CALCETrW2O0xFe733EVchVDXdJv3tazA=aXuBQ3fKfmHEwdZnLQ@mail.gmail.com> (raw)
In-Reply-To: <20200523155737.GC1189358@rani.riverdale.lan>
On Sat, May 23, 2020 at 8:57 AM Arvind Sankar <nivedita@alum.mit.edu> wrote:
>
> Hi,
>
> I have a question about the state of the upper 32 bits of the general
> purpose registers following a switch from/to 64-bit mode.
>
> Both the AMD [0] and Intel [1] manuals state that these bits are
> undefined following a switch from 64 to 32-bit mode. Since they can't be
> accessed in 32-bit mode, presumably this means they are undefined once
> you switch back to 64-bit mode and can see them again.
I would guess that all x86_64 CPUs actually preserve those registers
across mode changes and clear the high bits on 32-bit operations. But
making the kernel boot code more robust sounds entirely sensible to
me.
next prev parent reply other threads:[~2020-05-23 17:20 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-23 15:57 x86: Question about state of general purpose registers on switch to 64-bit mode Arvind Sankar
2020-05-23 17:19 ` Andy Lutomirski [this message]
2020-05-23 17:24 ` Linus Torvalds
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